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ADS1174 Datasheet(PDF) 7 Page - Texas Instruments |
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ADS1174 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 39 page CLK t CPW t CLK t CPW t SD t SCLK t DIST t DOHD t SPW Bit15(MSB) Bit14 Bit13 t SPW t DOPD t CD t DS t MSBPD t DIHD · · · t CONV DRDY SCLK DOUT DIN TIMING REQUIREMENTS: SPI FORMAT ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 TIMING CHARACTERISTICS: SPI FORMAT For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V. SYMBOL PARAMETER MIN TYP MAX UNIT tCLK CLK period (1/fCLK) (1) 37 10,000 ns tCPW CLK positive or negative pulse width 15 ns tCONV Conversion period (1/fDATA) (2) 256 2560 tCLK tCD (3) Falling edge of CLK to falling edge of DRDY 22 ns tDS (3) Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 tCLK tMSBPD DRDY falling edge to DOUT MSB valid (propagation delay) 16 ns tSD (3) Falling edge of SCLK to rising edge of DRDY 18 ns tSCLK (4) SCLK period 1 tCLK tSPW SCLK positive or negative pulse width 0.4 tCLK tDOHD (3) (5) SCLK falling edge to new DOUT invalid (hold time) 10 ns tDOPD (3) SCLK falling edge to new DOUT valid (propagation delay) 32 ns tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns tDIHD (5) Old DIN valid to falling edge of SCLK (hold time) 6 ns (1) fCLK = 27MHz maximum. (2) Depends on MODE[1:0] and CLKDIV selection. See Table 4 (fCLK/fDATA). (3) Load on DRDY and DOUT = 20pF. (4) For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. (5) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS1174 ADS1178 |
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