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ADS4129 Datasheet(PDF) 9 Page - Texas Instruments

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No. de pieza ADS4129
Descripción Electrónicos  14-/12-Bit, 160/250MSPS, Ultralow-Power ADC
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS4129 Datasheet(HTML) 9 Page - Texas Instruments

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ADS4126
, ADS4129
ADS4146
, ADS4149
www.ti.com
SBAS483F – NOVEMBER 2009 – REVISED OCTOBER 2010
ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and 0dB gain, unless otherwise noted.
Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and
DRVDD = 1.8V.
ADS4126/ADS4146 (160MSPS)
ADS4129/ADS4149 (250MSPS)
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage range
2
2
VPP
Differential input resistance (at dc); see Figure 114
> 1
> 1
M
Ω
Differential input capacitance; see Figure 115
4
4
pF
Analog input bandwidth
550
550
MHz
Analog input common-mode current (per input pin)
0.6
0.6
µA/MSPS
Common-mode output voltage
VCM
0.95
0.95
V
VCM output current capability
4
4
mA
DC ACCURACY
Offset error
–15
2.5
15
–15
2.5
15
mV
Temperature coefficient of offset error
0.003
0.003
mV/°C
Gain error as a result of internal reference
EGREF
–2
2
–2
2
%FS
inaccuracy alone
Gain error of channel alone
EGCHAN
–0.2
–0.2
–1
%FS
Temperature coefficient of EGCHAN
0.001
0.001
Δ%/°C
POWER SUPPLY
IAVDD
72
83
99
113
mA
Analog supply current
IDRVDD(1)
Output buffer supply current
39.5
51
47
mA
LVDS interface with 100
Ω external termination
Low LVDS swing (200mV)
IDRVDD
Output buffer supply current
51
63
59
72
mA
LVDS interface with 100
Ω external termination
Standard LVDS swing (350mV)
IDRVDD output buffer supply current(1)(2)
CMOS interface(2)
26
35
mA
8pF external load capacitance
fIN = 2.5MHz
Analog power
130
179
mW
LVDS interface, low LVDS swing
71.1
84.6
mW
Digital power
CMOS interface(2)
47
63
mW
8pF external load capacitance
fIN = 2.5MHz
Global power-down
10
25
10
25
mW
Standby
185
185
mW
(1)
The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the
maximum recommended load capacitance on each digital output line is 10pF.
(2)
In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
Copyright © 2009–2010, Texas Instruments Incorporated
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