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ADSP-BF514 Datasheet(PDF) 10 Page - Analog Devices

No. de pieza ADSP-BF514
Descripción Electrónicos  Blackfin Embedded Processor
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ADSP-BF514 Datasheet(HTML) 10 Page - Analog Devices

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Rev. PrE
|
Page 10 of 62
|
March 2009
ADSP-BF512/BF514/BF516/BF518(F)
Preliminary Technical Data
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the processor
from sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode or cause a transition from the hibernate
state.
Connect RTC signals RTXI and RTXO with external compo-
nents as shown in Figure 3.
WATCHDOG TIMER
The ADSP-BF512/BF514/BF516/BF518(F) processors include a
32-bit timer that can be used to implement a software watchdog
function. A software watchdog can improve system availability
by forcing the processor to a known state through generation of
a hardware reset, nonmaskable interrupt (NMI), or general-
purpose interrupt, if the timer expires before being reset by soft-
ware. The programmer initializes the count value of the timer,
enables the appropriate interrupt, then enables the timer.
Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are nine general-purpose programmable timer units in
the ADSP-BF512/BF514/BF516/BF518(F) processors. Eight
timers have an external signal that can be configured either as a
pulse width modulator (PWM) or timer output, as an input to
clock the timer, or as a mechanism for measuring pulse widths
and periods of external events. These timers can be synchro-
nized to an external clock input to the several other associated
PF signals, an external clock input to the PPI_CLK input signal,
or to the internal SCLK.
The timer units can be used in conjunction with the two UARTs
to measure the width of the pulses in the data stream to provide
a software auto-baud detect function for the respective serial
channels.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
3-PHASE PWM
Features of the 3-phase PWM generation unit are:
• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
• Single/double update modes
• Programmable dead time and switching frequency
• Twos-complement implementation which permits smooth
transition to full ON and full OFF states
• Possibility to synchronize the PWM generation to an exter-
nal synchronization
• Special provisions for BDCM operation (crossover and
output enable functions)
• Wide variety of special switched reluctance (SR) operating
modes
• Output polarity and clock gating control
• Dedicated asynchronous PWM shutdown signal
The processors integrate a flexible and programmable 3-phase
PWM waveform generator that can be programmed to generate
the required switching patterns to drive a 3-phase voltage
source inverter for ac induction (ACIM) or permanent magnet
synchronous (PMSM) motor control. In addition, the PWM
block contains special functions that considerably simplify the
generation of the required PWM switching patterns for control
of the electronically commutated motor (ECM) or brushless dc
motor (BDCM). Software can enable a special mode for
switched reluctance motors (SRM).
The six PWM output signals consist of three high-side drive sig-
nals (PWM_AH, PWM_BH, and PWM_CH) and three
low-side drive signals (PWM_AL, PWM_BL, and PWM_CL).
The polarity of the generated PWM signal be set with software,
so that either active HI or active LO PWM patterns can be
produced.
The switching frequency of the generated PWM pattern is pro-
grammable using the 16-bit PWMTM register. The PWM
generator can operate in single update mode or double update
Figure 3. External Components for RTCT
RTXO
C1
C2
X1
SUGGESTED COMPONENTS:
X1 = ECL IPTEK EC38J (THROUGH-HOLE PACKAGE) OR
EPSO N MC40512pF LOAD (SURFACE-MO UNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
R1 = 10 M
Ω
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECI FIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECI FI CATIO NS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
RTXI
R1


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