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ISL33003IUZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL33003IUZ Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 19 page 11 FN7560.2 September 30, 2010 to perform level shifting with the VCC1 and VCC2 supplies and provide capacitance buffering. Propagation Delays On a low to high transition, the rising edge signal is determined by the bus pull-up resistor, load capacitance, and the accelerator current from the ISL33001, ISL33002, ISL33003 buffer. Prior to the accelerators becoming active, the buffer is connected and the output voltage will track the input of the buffer. When the accelerators activate the buffer connection is released and the signal on each side of the buffer rises independently. The accelerator current on both sides of the buffer will be equal. If the pull-up resistance on both sides of the buffer are also equal, then differences in the rise time will be proportional to the difference in capacitive loading on the two sides. Because the signals on each side of the buffer rise independently, the propagation delay can be positive or negative. If the input side rises slowly relative to the output (i.e., heavy capacitive loading on the input and light load on the output) then the propagation delay tPLH is negative. If the output side rises slowly relative to the input, tPLH is positive. For high to low transitions, there is a finite propagation delay through the buffer from the time an external low on the input drives the NMOS output low. This propagation delay will always be positive because the buffer connect threshold on the falling edge is below the measurement points of the delay. In addition to the propagation delay of the buffer, there will be additional delay from the different capacitive loading of the buffer. Figures 21 and 22 show how the propagation delay from high to low, tPHL, is affected by VCC and capacitive loading. The buffer’s propagation delay times for rising and falling edge signals must be taken into consideration for the timing requirements of the system. SETUP and HOLD times may need to be adjusted to take into account excessively long propagation delay times caused by heavy bus capacitances. Pull-Up Resistor Selection While the ISL33001, ISL33002, ISL33003 2-Channel buffers are designed to improve the rise time of the bus in passive pull-up systems, proper selection of the pull-up resistor is critical for system operation when a buffer is used. For a bus that is operating normally without active rise time circuitry, using the ISL33001, ISL33002, ISL33003 buffer will allow larger pull-up resistor values to reduce sink currents when the bus is driving low. However, choose a pull-up resistor value of no larger than 20kΩ regardless of the bus capacitance seen on the SDA/SCL lines. The Bus Idle or Stop Bit condition requires valid logic high voltages to give a valid connection state. Pull-up resistor values 20kΩ or smaller are recommended to overcome the typical 150kΩ impedance of the pre-charge circuitry, delivering valid high levels. Typical Performance Curves C IN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25°C; Unless Otherwise Specified. FIGURE 9. ICC1 ENABLED CURRENT vs VCC1 (ISL33001) FIGURE 10. ICC1 DISABLED CURRENT vs VCC1 (ISL33001) VCC1 (V) 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 T = +85°C T = +25°C T = -40°C VCC1 (V) 100 150 200 250 300 350 400 450 500 550 600 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 T = +85°C T = +25°C ISL33001, ISL33002, ISL33003 |
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