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ISL12022IBZ Datasheet(PDF) 4 Page - Intersil Corporation |
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ISL12022IBZ Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 28 page  4 FN6659.2 June 23, 2009 Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. SYMBOL PARAMETER CONDITIONS MIN (Note 9) TYP (Note 5) MAX (Note 9) UNITS NOTES VDD SR- VDD Negative Slew rate 10 V/ms 6 I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 9) TYP (Note 5) MAX (Note 9) UNITS NOTES VIL SDA and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V VIH SDA and SCL Input Buffer HIGH Voltage 0.7 x VDD VDD + 0.3 V Hysteresis SDA and SCL Input Buffer Hysteresis 0.05 x VDD V7, 8 VOL SDA Output Buffer LOW Voltage, Sinking 3mA VDD = 5V, IOL = 3mA 0 0.02 0.4 V CPIN SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz, VDD = 5V, VIN =0V, VOUT = 0V 10 pF 7, 8 fSCL SCL Frequency 400 kHz tIN Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge To SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VDD. 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD. 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. 0 900 ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. 600 ns ISL12022 |
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