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ADL5502ACBZ-P2 Datasheet(PDF) 7 Page - Analog Devices

No. de pieza ADL5502ACBZ-P2
Descripción Electrónicos  450 MHz to 6000 MHz Crest Factor Detector
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Fabricante Electrónico  AD [Analog Devices]
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ADL5502ACBZ-P2 Datasheet(HTML) 7 Page - Analog Devices

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ADL5502
Rev. A | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
7
6
5
4
8
TOP VIEW
(BALL SIDE DOWN)
BALL A1
CORNER
FLTR
VPOS
RFIN
VRMS
PEAK
CNTL
COMM
ENBL
ADL5502
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
FLTR
Modulation Filter Pin. Connection for an external capacitor to lower the corner frequency of the modulation filter.
2
VPOS
Supply Voltage Pin. Operational range 2.5 V to 3.3 V.
3
RFIN
Signal Input Pin. Internally ac-coupled after internal termination resistance. Nominal 500 Ω input impedance.
4
COMM
Device Ground Pin.
5
CNTL
Control Pin. Connect pin to ground for peak-hold mode. Connect pin to VS for reset mode (tracking envelope).
To measure the peak of a waveform, the control pin must be briefly set to high (reset mode for >1 μs) to start at a
known state.
6
PEAK
Envelope Peak Output. Voltage output for peak-hold function, with limited current drive capability. The output
has an internal 100 Ω series resistance. Low capacitance loads are recommended to allow for envelope tracking
and fast response time.
7
VRMS
RMS Output Pin. Rail-to-rail voltage output with limited current drive capability. The output has an internal 100 Ω
series resistance. High resistive loads and low capacitance loads are recommended to preserve output swing and
allow fast response.
8
ENBL
Enable Pin. Connect pin to VS for normal operation. Connect pin to ground for disable mode.


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