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LC662304A Datasheet(Hoja de datos) 5 Page - Sanyo Semicon Device

No. de Pieza. LC662304A
Descripción  Four-Bit Single-Chip Microcontrollers with 4, 6, 8, 12, and 16 KB of On-Chip ROM
Descarga  25 Pages
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Fabricante  SANYO [Sanyo Semicon Device]
Página de inicio  http://www.ssdc-jp.com/eng/
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 5 page
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Pin Function Overview
No. 5483-5/25
LC662304A, 662306A, 662308A, 662312A, 662316A
Pin
I/O
Overview
Output driver type
Options
State after a Standby mode
reset
operation
P00
P01
P02
P03
P10
P11
P12
P13
P20/SI0
P21/SO0
P22/SCK0
P23/INT0
P30/INT1
P31/POUT0
P32/POUT1
P33/HOLD
P40/INV0I
P41/INV0O
P42/INV1I
P43/INV1O
I/O ports P00 to P03
• Input or output in 4-bit or 1-bit units
• P00 to P03 support the halt mode
control function (This function can be
specified in bit units.)
I/O ports P10 to P13
Input or output in 4-bit or 1-bit units
I/O ports P20 to P23
• Input or output in 4-bit or 1-bit units
• P20 is also used as the serial input SI0
pin.
• P21 is also used as the serial output
SO0 pin.
• P22 is also used as the serial clock
SCK0 pin.
• P23 is also used as the INT0 interrupt
request pin, and also as the timer 0
event counting and pulse width
measurement input.
I/O ports P30 to P32
• Input or output in 3-bit or 1-bit units
• P30 is also used as the INT1 interrupt
request.
• P31 is also used for the square wave
output from timer 0.
• P32 is also used for the square wave
and PWM output from timer 1.
• P31 and P32 also support 3-state
outputs.
Hold mode control input
• Hold mode is set up by the HOLD
instruction when HOLD is low.
• In hold mode, the CPU is restarted by
setting HOLD to the high level.
• This pin can be used as input port P33
along with P30 to P32.
• When the P33/HOLD pin is at the low
level, the CPU will not be reset by a
low level on the RES pin. Therefore,
applications must not set P33/HOLD
low when power is first applied.
I/O ports P40 to P43
• Input or output in 4-bit or 1-bit units
• Input or output in 8-bit units when used
in conjunction with P50 to P53.
• Can be used for output of 8-bit ROM
data when used in conjunction with
P50 to P53.
• Dedicated inverter circuit (option)
I/O
I/O
I/O
I/O
I
I/O
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +12-V handling when
OD option selected
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +12-V handling when
OD option selected
• Pch: Pull-up MOS type
• CMOS type when the inverter
circuit option is selected
• Nch: Intermediate sink current
type
• Pull-up MOS or
Nch OD output
• Output level on
reset
• Pull-up MOS or
Nch OD output
• Output level on
reset
CMOS or Nch OD
output
CMOS or Nch OD
output
• Pull-up MOS or
Nch OD output
• Output level on
reset
• Inverter circuit
High or low
(option)
High or low
(option)
H
H
High or low
or inverter
I/O (option)
Hold mode:
Output off
Hold mode:
Output off
Hold mode:
Output off
Hold mode:
Output off
Hold mode:
Port output
off, inverter
output off
Halt mode:
Port output
retained,
inverter
output
continues
Halt mode:
Output
retained
Halt mode:
Output
retained
Halt mode:
Output
retained
Halt mode:
Output
retained
Continued on next page.




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