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LC66354C Datasheet(PDF) 19 Page - Sanyo Semicon Device

No. de pieza LC66354C
Descripción Electrónicos  Four-Bit Single-Chip Microcontrollers with 4, 6, and 8 KB of On-Chip ROM
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Fabricante Electrónico  SANYO [Sanyo Semicon Device]
Página de inicio  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC66354C Datasheet(HTML) 19 Page - Sanyo Semicon Device

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Continued from preceding page.
No. 5484-19/21
LC66354C, 66356C, 66358C
Continued on next page.
Instruction code
Affected
Mnemonic
Operation
Description
status
Note
D7 D6 D5 D4 D3 D2 D1 D0
bits
[Branch instructions]
PC7 to 0
Branch to the location in the
BC addr
Branch on CF
1101
1100
22
P7 P6 P5 P4
same page specified by P7 to
P7 P6 P5 P4 P3 P2 P1 P0
P3 P2 P1 P0
P0 if CF is one.
if (CF) = 1
PC7 to 0
Branch to the location in the
BNC
Branch on no CF
1001
1100
22
P7 P6 P5 P4
same page specified by P7 to
addr
P7 P6 P5 P4 P3 P2 P1 P0
P3 P2 P1 P0
P0 if CF is zero.
if (CF) = 0
PC7 to 0
Branch to the location in the
BZ addr
Branch on ZF
1101
1101
22
P7 P6 P5 P4
same page specified by P7 to
P7 P6 P5 P4 P3 P2 P1 P0
P3 P2 P1 P0
P0 if ZF is one.
if (ZF) = 1
PC7 to 0
Branch to the location in the
BNZ
Branch on no ZF
1001
1101
22
P7 P6 P5 P4
same page specified by P7 to
addr
P7 P6 P5 P4 P3 P2 P1 P0
P3 P2 P1 P0
P0 if ZF is zero.
if (ZF) = 0
PC7 to 0
Branch to the location in the
BFn4
1111
n3 n2 n1 n0
P7 P6 P5 P4
same page specified by P0 to
addr
Branch on flag bit
P7 P6 P5 P4 P3 P2 P1 P0
22
P3 P2 P1 P0
P7 if the flag (of the 16 user
if (Fn) = 1
flags) specified by n3 n2 n1 n0
is one.
PC7 to 0
Branch to the location in the
BNFn4
1011
n3 n2 n1 n0
P7 P6 P5 P4
same page specified by P0 to
addr
Branch on no flag bit
P7 P6 P5 P4 P3 P2 P1 P0
22
P3 P2 P1 P0
P7 if the flag (of the 16 user
if (Fn) = 0
flags) specified by n3 n2 n1 n0
is zero.
[I/O instructions]
IP0
Input port 0 to AC
0010
0000
1
1
AC
← (P0)
Input the contents of port
ZF
0 to AC.
IP
Input port to AC
0010
0110
1
1
AC
← [P (DP
L)]
Input the contents of port
ZF
P (DPL) to AC.
IPM
Input port to M
0001
1001
1
1
M (HL)
← [P (DP
L)]
Input the contents of port
P (DPL) to M (HL).
IPDR i4
Input port to
1100
1111
2
2
AC
← [P (i4)]
Input the contents of
ZF
AC direct
0110
I3 I2 I1 I0
P (i4) to AC.
Input port 4, 5 to
1100
1111
E
← [P (4)]
Input the contents of ports
IP45
E, AC respectively
1101
0100
22
AC
← [P (5)]
P (4) and P (5) to E and AC
respectively.
OP
Output AC to port
0010
0101
1
1
P (DPL) ← (AC)
Output the contents of AC to
port P (DPL).
OPM
Output M to port
0001
1010
1
1
P (DPL) ← [M (HL)]
Output the contents of M (HL)
to port P (DPL).
OPDR i4
Output AC to
1100
1111
2
2
P (i4)
← (AC)
Output the contents of AC
port direct
0111
I3 I2 I1 I0
to P (i4).
Output E, AC to port
1100
1111
P (4)
← (E)
Output the contents of E and
OP45
4, 5 respectively
1101
0101
22
P (5)
← (AC)
AC to ports P (4) and P (5)
respectively.
Set to one the bit in port
SPB t2
Set port bit
0000
10 t1 t0
1
1
[P (DPL), t2] ← 1
P (DPL) specified by the
immediate data t1 t0.
Clear to zero the bit in port
RPB t2
Reset port bit
0010
10 t1 t0
1
1
[P (DPL), t2] ← 0
P (DPL) specified by the
ZF
immediate data t1 t0.
And port with
P (P3 to P0) ←
Take the logical AND of P (P3
ANDPDR
immediate data then
1100
0101
2
2
[P (P3 to P0)]
to P0) and the immediate data
ZF
i4, p4
output
I3 I2 I1 I0 P3 P2 P1 P0
I3 to I0
I3 I2 I1 I0 and output the result
to P (P3 to P0).
Or port with
P (P3 to P0) ←
Take the logical OR of P (P3
ORPDR
immediate data then
1100
0100
2
2
[P (P3 to P0)]
to P0) and the immediate data ZF
i4, p4
output
I3 I2 I1 I0 P3 P2 P1 P0
I3 to I0
I3 I2 I1 I0 and output the result
to P (P3 to P0).


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