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LC66P408 Datasheet(PDF) 7 Page - Sanyo Semicon Device |
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LC66P408 Datasheet(HTML) 7 Page - Sanyo Semicon Device |
7 / 17 page No. 5997-7/17 LC662508A, 662512A, 662516A Pin I/O Overview Output driver type Options State after a Standby mode reset operation PD0/INV3I PD1/INV3O PD2/INV4I PD3/INV4O PE0 PE1 OSC1 OSC2 RES TEST VDD VSS Dedicated input ports PD0 to PD3 Dedicated inverter circuits (option) Dedicated input ports System clock oscillator connections When an external clock is used, leave OSC2 open and connect the clock signal to OSC1. System reset input When the P33/HOLD pin is at the high level, a low level input to the RES pin will initialize the CPU. CPU test pin This pin must be connected to VSS during normal operation. Power supply pins I I I O I I • When the inverter circuit option is selected. • Pch: CMOS type • Nch: Intermediate sink current type Inverter circuits Ceramic oscillator or external clock selection Normal input or inverter I/O (option) Option selection Inverter • Hold mode: output off • Halt mode: output continues Hold mode: input disabled Halt mode: input enabled Hold mode: Oscillator stops Halt mode: Oscillator continues Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD. CMOS output: Complementary output. OD output: Open-drain output Continued from preceding page. User Options 1. Ports 0, 1, 4, 5, and 8 output level at reset option The output levels at reset for I/O ports 0, 1, 4, 5, and 8 in independent 4-bit groups, can be selected from the following two options. 2. Oscillator circuit options • Main clock Option Circuit Conditions and notes External clock Ceramic oscillator The input has Schmitt characteristics Option Conditions and notes Output high at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group Output low at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group OSC1 OSC1 OSC2 C1 C2 Ceramic oscillator Note: There is no RC oscillator option. |
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