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LC665304A Datasheet(PDF) 14 Page - Sanyo Semicon Device |
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LC665304A Datasheet(HTML) 14 Page - Sanyo Semicon Device |
14 / 26 page Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified. Note: 1. Applies to pins with open-drain specifications. However, VIH2 applies to the P33/HOLD pin. When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins. 2. PC port pins with CMOS output specifications cannot be used as input pins. Contact your Sanyo representative for the allowable operating ranges for P4, PC, and PD when the inverter array is used, and for P8 when the buffer array is used. 3. Applies to pins with open-drain specifications. However, VIL3 applies to the P33/HOLD pin. P2, P3, and P6 port pins with CMOS output specifications cannot be used as input pins. No. 5485-14/26 LC665304A, 665306A, 665308A, 665312A, 665316A Parameter Symbol Conditions min typ max Unit Note Operating supply voltage VDD VDD 3.0 5.5 V Memory retention supply voltage VDDHVDD: During hold mode 1.8 5.5 V VIH1 P2, P3 (except for the P33/HOLD pin), 0.8 VDD +7.0 V 1 P61, and P63: N-channel output transistor off Input high-level voltage VIH2 P33/HOLD, P60, P62, RES, OSC1: 0.8 VDD VDD V1 N-channel output transistor off VIH3 P0, P1, P4, P5, PC, PD, PE: 0.8 VDD VDD V2 N-channel output transistor off VIL1 P2, P3 (except for the P33/HOLD pin), P6, VSS 0.2 VDD V3 RES, and OSC1: N-channel output transistor off Input low-level voltage VIL2 P0, P1, P4, P5, PC, PD, PE, TEST: VSS 0.2 VDD V2 N-channel output transistor off VIL3 P33/HOLD: VDD = 1.8 to 5.5 V VSS 0.2 VDD V When the main oscillator is operating 0.4 4.20 MHz Operating frequency fop (10) (0.95) (µs ) (instruction cycle time) (Tcyc) When the sub-oscillator is operating 30 32.768 100 kHz (133) (122) (25) (µs) [External clock input conditions] OSC1: Defined by Figure 1. Input the clock Frequency fext signal to OSC1 and leave OSC2 open. 0.4 4.20 MHz (External clock input must be selected as the oscillator circuit option.) OSC1: Defined by Figure 1. Input the clock Pulse width textH, textL signal to OSC1 and leave OSC2 open. 100 ns (External clock input must be selected as the oscillator circuit option.) OSC1: Defined by Figure 1. Input the clock Rise and fall times textR, textF signal to OSC1 and leave OSC2 open. 30 ns (External clock input must be selected as the oscillator circuit option.) |
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Descripción similar - LC665304A |
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