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LC665304A Datasheet(PDF) 23 Page - Sanyo Semicon Device |
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LC665304A Datasheet(HTML) 23 Page - Sanyo Semicon Device |
23 / 26 page Continued from preceding page. No. 5485-23/26 LC665304A, 665306A, 665308A, 665312A, 665316A Instruction code Affected Mnemonic Operation Description status Note D7 D6 D5 D4 D3 D2 D1 D0 bits [Jump and subroutine instructions] Store the contents of reg in M2 (SP). Subtract 2 from SP after the store. PUSH Push reg on M2 (SP) 1100 1111 22 M2 (SP) ← (reg) reg 1111 1 i1 i0 0 SP ← (SP) – 2 Add 2 to SP and then load the POP 1100 1111 SP ← (SP) + 2 contents of M2(SP) into reg. reg Pop reg off M2 (SP) 1110 1 i1 i0 0 22 reg ← [M2 (SP)] The relation between i1i0 and reg is the same as that for the PUSH reg instruction. Return from SP ← (SP) + 4 Return from a subroutine or RT subroutine 0001 1100 1 2 PC ← [M4 (SP)] interrupt handling routine. ZF and CF are not restored. Return from interrupt SP ← (SP) + 4 Return from a subroutine or RTI routine 0001 1101 1 2 PC ← [M4 (SP)] interrupt handling routine. ZF ZF, CF CF, ZF ← [M4 (SP)] and CF are restored. [Branch instructions] PC7 to 0 ← Branch to the location in the BAt2 Branch on AC bit 1101 00 t1 t0 22 P7 P6 P5 P4 same page specified by P7 to addr P7 P6 P5 P4 P3 P2 P1 P0 P3 P2 P1 P0 P0 if the bit in AC specified by if (AC, t2) = 1 the immediate data t1 t0 is one. PC7 to 0 ← Branch to the location in the BNAt2 Branch on no AC bit 1001 00 t1 t0 22 P7 P6 P5 P4 same page specified by P7 to addr P7 P6 P5 P4 P3 P2 P1 P0 P3 P2 P1 P0 P0 if the bit in AC specified by if (AC, t2) = 0 the immediate data t1 t0 is zero. PC7 to 0 ← Branch to the location in the BMt2 1101 01 t1 t0 P7 P6 P5 P4 same page specified by P7 to addr Branch on M bit P7 P6 P5 P4 P3 P2 P1 P0 22 P3 P2 P1 P0 P0 if the bit in M (HL) specified if [M (HL),t2] by the immediate data t1 t0 = 1 is one. PC7 to 0 ← Branch to the location in the BNMt2 1001 01 t1 t0 P7 P6 P5 P4 same page specified by P7 to addr Branch on no M bit P7 P6 P5 P4 P3 P2 P1 P0 22 P3 P2 P1 P0 P0 if the bit in M (HL) specified if [M (HL),t2] by the immediate data t1 t0 = 0 is zero. Internal control registers can also be tested by PC7 to 0 ← Branch to the location in the executing this P7 P6 P5 P4 same page specified by P7 to instruction BPt2 Branch on Port bit 1101 10 t1 t0 22 P3 P2 P1 P0 P0 if the bit in port (DPL) immediately after addr P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] specified by the immediate a BANK = 1 data t1 t0 is one. instruction. However, this is limited to registers that can be read out. Internal control registers can also be tested by PC7 to 0 ← Branch to the location in the executing this P7 P6 P5 P4 same page specified by P7 to instruction BNPt2 Branch on no Port bit 1001 10 t1 t0 22 P3 P2 P1 P0 P0 if the bit in port (DPL) immediately after addr P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] specified by the immediate a BANK = 0 data t1 t0 is zero. instruction. However, this is limited to registers that can be read out. Continued on next page. reg i1 i0 HL 0 0 XY 0 1 AE 1 0 Illegal value 1 1 |
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