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LC723732 Datasheet(PDF) 13 Page - Sanyo Semicon Device

No. de Pieza. LC723732
Descripción  ETR Microcontrollers
Descarga  14 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  SANYO [Sanyo Semicon Device]
Página de inicio  https://www.sanyo-av.com/us/
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LC723732 Datasheet(HTML) 13 Page - Sanyo Semicon Device

 
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 13 / 14 page
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No. 5931-13/14
LC723732/40/48/56/64
Continued from preceding page.
Mnemonic
Operand
Function
Operations function
Instruction format
1st
2nd
AND
r
M
AND M with r
r
← (r) AND (M)
0 0 1 0 0 0 DH
DL
r
ANDI
M
I
AND I with M
M
← (M) AND I
0 0 1 0 0 1 DH
DL
I
OR
r
M
OR M with r
r
← (r) OR (M)
0 0 1 0 1 0 DH
DL
r
ORI
M
I
OR I with M
M
← (M) OR I
0 0 1 0 1 1 DH
DL
I
EXL
r
M
Exclusive OR M with r
r
← (r) XOR (M)
0 0 1 1 0 0 DH
DL
r
EXLI
M
I
Exclusive OR M with M
M
← (M) XOR I
0 0 1 1 0 1 DH
DL
I
SHMR
M
Shift M right with carry
1 1 1 1 1 1 1 1 1 0 DH
DL
LD
r
M
Load M to r
r
← (M)
1 1 0 1 0 0 DH
DL
r
ST
M
r
Strore r to M
M
← (r)
1 1 0 1 0 1 DH
DL
r
LDA
r
Load M specified by ADR to r
r
← (MADR)
1 1 1 1 1 0 0 1 1 1 0 0
r
STA
r
Store r to M specified by ADR
MADR ← (r)
1 1 1 1 1 0 0 1 1 1 0 1
r
MVRD
r
M
Move M to destination M referring to r in
[DH, rn]
← (M)
1 1 0 1 1 0 DH
DL
r
the same row
MVRS
M
r
Move source M referring to r to M in the
M
← (DH, rn)
1 1 0 1 1 1 DH
DL
r
same row
MVSR
M1
M2
Move M to M in the same row
[DH, DL1]
← [DH, DL2]
1 1 1 0 0 0 DH
DL
DL2
MVI
M
I
Move I to M
M
← I
1 1 1 0 0 1 DH
DL
I
TMT
M
N
Test M bits, then skip if all bits specified
if M(N) = all 1, then skip
1 1 1 1 0 0 DH
DL
N
are true
TMF
M
N
Test M bits, then skip if all bits specified
if M(N) = all 0, then skip
1 1 1 1 0 1 DH
DL
N
are false
JMP
ADDR
Jump to the address
PC
← ADDR
1 0
ADDR(14 bits)
JMPA
Jump to the address specified by ADR
PC
← (ADR)
0 0 0 0 0 0 0 0 1 1 1 0
JMPR
ADDR
Jump to the relative address
PC
← (PC) + 1 + ADDR
1 1 1 1 1 0 1 0
ADDR (8 bits)
CAL
ADDR
Call subroutine
PC
← ADDR
1 1 0 0
ADDR(12 bits)
Stack
← (PC) + 1
CALA
Call subroutine specified by ADR
PC
← (ADR)
0 0 0 0 0 0 0 0 1 1 1 1
Stack
← (PC) + 1
RT
Return from subroutine
PC
← Stack
0 0 0 0 0 0 0 0 1 0 0 0
RTS
Return from subroutine and skip
PC
← Stack + 1
0 0 0 0 0 0 0 0 1 0 1 0
RTB
Return from subroutine with BANK data
PC
← Stack,
1 1 1 1 1 1 1 1 1 1 0 0
BANK
← Stack
RTBS
Return from subroutine with BANK data
PC
← Stack + 1,
1 1 1 1 1 1 1 1 1 1 0 1
and skip
BANK
← Stack
PC
← Stack,
RTI
Return from interrupt
BANK
← Stack,
0 0 0 0 0 0 0 0 1 0 0 1
CARRY
← Stack
PAGE
← Stack
SS
SWR
N
Set status register
(Status W-reg)N
← 1
1 1 1 1 1 1 1 1 0 0 SWR
N
RS
SWR
N
Reset status register
(Status W-reg)N
← 0
1 1 1 1 1 1 1 1 0 1 SWR
N
TST
SRR
N
Test status register true
if (Status R-reg)N = all1, then skip 1 1 1 1 1 0 0 0 0
SRR
N
TSF
SRR
N
Test status register false
if (Status R-reg)N = all0, then skip 1 1 1 1 1 0 0 0 1
SRR
N
PLL
M
Load M to PLL register
PLL reg
← PLL data
1 1 1 1 1 0 0 1 0 1 DH
DL
PUT
PEn
Put data of DTR to perifheral register
PEn
← (DTR)
1 1 1 1 1 0 0 1 1 0 1 0
PEn
GET
PEn
Get peripheral data to DTR
DTR
← (PEn)
1 1 1 1 1 0 0 1 1 0 1 1
PEn
SIO
I1
I2
Serial I/O control
SIO reg
← I1, I2
0 0 0 0 0 0 0 1
I1
I2
UCS
I
Set I to UCCW1
UCCW1
← I
0 0 0 0 0 0 0 0 0 0 0 1
I
UCC
I
Set I to UCCW2
UCCW2
← I
0 0 0 0 0 0 0 0 0 0 1 0
I
BEEP
I
Beep control
BEEP reg
← I
0 0 0 0 0 0 0 0 0 1 1 0
I
DZC
I
Dead zone control
DZC reg
← I
0 0 0 0 0 0 0 0 1 0 1 1
I
TMS
I
Set timer register
Timer reg
← I
0 0 0 0 0 0 0 0 1 1 0 0
I
IOS1
PW1n
N
Set port control word1
IOS1 reg PW1n
← N
1 1 1 1 1 1 1 0
PW1n
N
IOS2
PW2n
N
Set port control word2
IOS2 reg PW2n
← N
1 1 1 1 1 0 1 1
PW2n
N
f e d c b a 9 8 7 6 5 4 3 2 1 0
carry
(M)
Continued on next page.


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