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LC723732 Datasheet(PDF) 14 Page - Sanyo Semicon Device

No. de Pieza. LC723732
Descripción  ETR Microcontrollers
Descarga  14 Pages
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Fabricante  SANYO [Sanyo Semicon Device]
Página de inicio  https://www.sanyo-av.com/us/
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LC723732 Datasheet(HTML) 14 Page - Sanyo Semicon Device

 
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PS No. 5931-14/14
LC723732/40/48/56/64
This catalog provides information as of June, 1998. Specifications and information herein are subject to change
without notice.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s Anyone purchasing any products described or contained herein for an above-mentioned use shall:
ΠAccept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Continued from preceding page.
Mnemonic
Operand
Function
Operations function
Instruction format
1st
2nd
IN
M
P1n
Input port1 data to M
M
← (P1n)
1 1 1 0 1 0 DH
DL
P1n
OUT
M
P1n
Output contents of M to port 1
P1n
← M
1 1 1 0 1 1 DH
DL
P1n
INR
M
P2n
Input port 2 data to M
M
← (P2n)
0 0 1 1 1 0 DH
DL
P2n
OUTR
M
P2n
Output contents of M to port 2
P2n
← (M)
0 0 1 1 1 1 DH
DL
P2n
SPB
P1n
N
Set port 1 bits
(P1n)N
← 1
0 0 0 0 0 0 1 0
P1n
N
RPB
P1n
N
Reset port 1 bits
(P1n)N
← 0
0 0 0 0 0 0 1 1
P1n
N
TPT
P1n
N
Test port 1 bits, then skip if all bits
if (P1n)N = all 1, then skip
1 1 1 1 1 1 0 0
P1n
N
specified are true
TPF
P1n
N
Test port 1 bits, then skip if all bits
if (P1n)N = all 0, then skip
1 1 1 1 1 1 0 1
P1n
N
specified are false
BANK
I
Select Bank
BANK
← I
1 1 1 1 1 0 0 1 0 0
I
MVTL
Move program memory data specified by
DTR
← (ROMADR)
0 0 0 0 0 0 0 0 0 0 1 1
ADR to DTR
PUSH
SR
Move ADR/DTR to stack
Stack
← (ADR/DTR)
1 1 1 1 1 0 0 1 1 0 0 0
SR
POP
SR
Move stack to ADR/DTR
ADR/DTR
← Stack
1 1 1 1 1 0 0 1 1 0 0 1
SR
PAGE
I
Set page flag
PAGE flag
← I
0 0 0 0 0 0 0 0 0 1 1 1
I
HALT
I
Halt mode control
HALT reg
← I,
0 0 0 0 0 0 0 0 0 1 0 0
I
then CPU clock stop
CKSTP
Clock stop
Stop xtal OSC if HOLD = 0
0 0 0 0 0 0 0 0 0 1 0 1
NOP
No operation
No operation
0 0 0 0 0 0 0 0 0 0 0 0
f e d c b a 9 8 7 6 5 4 3 2 1 0


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