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LC723732 Datasheet(PDF) 6 Page - Sanyo Semicon Device

No. de Pieza. LC723732
Descripción  ETR Microcontrollers
Descarga  14 Pages
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Fabricante  SANYO [Sanyo Semicon Device]
Página de inicio  http://www.ssdc-jp.com/eng/
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LC723732 Datasheet(HTML) 6 Page - Sanyo Semicon Device

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No. 5931-6/14
LC723732/40/48/56/64
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
IIH1
XIN: VI = VDD = 5.0 V
2.0
5.0
15
µA
IIH2
FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V
4.0
10
30
µA
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL,
PM, PN, PO, PP, PQ, PR, PS, PT-PORT,
SNS, HOLD, RESET, HCTR, LCTR, E03,
Input high-level current
IIH3
SUBPD: VI = VDD = 5.0 V
3.0
µA
(With the port PA pull-down resistors disabled,
and PB, PC, PD, PE, PF, PG, PK, PL, PM,
PN, PP, PO, PQ, PR, PS, and PT ports set to
input mode.)
IIH4
Port PA (pull-down resistors enabled):
50
µA
VI = VDD = 5.0 V
IIL1
XIN: VI = VSS
2.0
5.0
15
µA
IIL2
FMIN, AMIN, HCTR, LCTR: VI = VSS
4.0
10
30
µA
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL,
PM, PN, PO, PP, PQ, PR, PS, PT-PORT,
Input low-level current
SNS, HOLD, RESET, HCTR, LCTR, E03,
IIL3
SUBPD: VI = VSS
3.0
µA
(With the port PA pull-down resistors disabled,
and PB, PC, PD, PE, PF, PG, PK, PL, PM,
PN, PP, PO, PQ, PR, PS, and PT ports set to
input mode.)
Input floating voltage
VIF
Port PA (pull-down resistors enabled)
0.05 VDD
V
Hysteresis
VH
PD, PE, PF, PG, PK-PORT, RESET,
0.1 VDD
0.2 VDD
V
LCTR(in period measurement mode)
VOH1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO,
VDD – 1.0
V
Output high-level voltage
PP, PQ, PR, PS, PT-PORT: IO = –1 mA
VOH2
EO1, EO2, EO3, SUBPD: IO = –500 µA
VDD – 1.0
V
VOH3
XOUT: IO = –200 µA
VDD – 1.0
V
VOL1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO,
1.0
V
PP, PQ, PR, PS, PT-PORT: IO = 1 mA
Output low-level voltage
VOL2
E01, E02, E03, SUBPD: IO = 500 µA
1.0
V
VOL3
XOUT: IO = 200 µA
1.5
V
VOL4
PC, PJ-PORT: IO = 5 mA
2.0
V
IOFF1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO,
–3.0
3.0
µA
Output off leakage current
PP, PQ, PR, PS, PT-PORT
IOFF2
E01, E02, E03, SUBPD
–100
100
nA
IOFF3
PC, PJ-PORT
–5.0
5.0
µA
A/D conversion error
ADI0 to ADI7 VDD1
–1.5
1.5
LSB
Rejected pulse width
PREJ
SNS
50
µsec
Power down detection voltage
VDET
2.6
3.0
3.4
V
RPD1
Port PA (pull-down resistors enabled):
75
100
200
k
Pull-down resistance
VDD = 5 V
RPD2
TEST1, TEST2
10
k
IDD1
During normal operation (PLL operating)
20
30
mA
VDD1, fIN2 = 130 MHz Ta = 25°C
Halt mode (CPU operation stopped, crystal
IDD2
oscillator operating) (See figure 1.)
0.45
mA
Current drain
VDD2, Ta = 25°C*
IDD3
Backup mode (crystal oscillator stopped)
5
µA
(See figure 2.) VDD = 5.5 V, Ta = 25°C
IDD4
Backup mode (crystal oscillator stopped)
1
µA
(See figure 2.) VDD = 2.5 V, Ta = 25°C
Electrical Characteristics in the allowable operating ranges
Note *: Twenty instruction steps are executed every millisecond. The PLL, universal counter, and other functions are stopped.


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