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K20P100M100SF2 Datasheet(PDF) 25 Page - Freescale Semiconductor, Inc |
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K20P100M100SF2 Datasheet(HTML) 25 Page - Freescale Semiconductor, Inc |
25 / 65 page Table 13. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes fdco_t_DMX3 2 DCO output frequency Low range (DRS=00) 732 × ffll_ref — 23.99 — MHz 4, 5 Mid range (DRS=01) 1464 × ffll_ref — 47.97 — MHz Mid-high range (DRS=10) 2197 × ffll_ref — 71.99 — MHz High range (DRS=11) 2929 × ffll_ref — 95.98 — MHz Jcyc_fll FLL period jitter — TBD TBD ps 6 Jacc_fll FLL accumulated jitter of DCO output over a 1µs time window — TBD TBD ps 6 tfll_acquire FLL target frequency acquisition time — — 1 ms 7 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current • PLL @ 96 MHz (fosc_hi_1=8MHz, fpll_ref=2MHz, VDIV multiplier=48) — 950 — µA 8 fpll_ref PLL reference frequency range 2.0 — 4.0 MHz Jcyc_pll PLL period jitter — 400 — ps 9, 10 Jacc_pll PLL accumulated jitter over 1µs window — TBD — ps 9, 10 Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 0.15 + 1075(1/ fpll_ref) ms 11 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation ( Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification was obtained at TBD frequency. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification was obtained at internal frequency of TBD. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 25 |
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