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LC78628 Datasheet(Hoja de datos) 4 Page - Sanyo Semicon Device

No. de Pieza. LC78628
Descripción  Compact Disc Player DSP with Built-in HDCD Decoder
Descarga  40 Pages
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Fabricante  SANYO [Sanyo Semicon Device]
Página de inicio  http://www.ssdc-jp.com/eng/
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 4 page
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No. 6329-4/40
LC78628E
Continued from preceding page.
Notes: The same voltage must be applied to all 5 V system power supply pins.
* When used in conjunction with an ASP that provides a command interface, the stricter ratings of the ASP shall be given priority.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input level
VIN1
EFMIN: Slice level control
1.0
Vp-p
VIN2
XIN: Capacitor coupled input
1.0
Vp-p
Data setup time
tSU
COIN, RWC, *: See figure 1.
400
ns
Data hold time
tHD
COIN, RWC, *: See figure 1.
400
ns
High-level clock pulse width
tWH
CQCK, *: See figures 1 and 2.
400
ns
Low-level clock pulse width
tWL
CQCK, *: See figures 1 and 2.
400
ns
Data read access time
tRAC
SQOUT: See figures 2.
0
400
ns
Command output time
tRWC
RWC, *: See figures 1.
1000
ns
Subcode Q readout enable time
tSQE
WRQ, normal speed: See figures 2, RWC = VIL1
11.2
ms
Port input setup time
tCSU
P0 to P4, RWC: See figures 3.
400
ns
Port input hold time
tCHD
P0 to P4, RWC: See figures 3.
400
ns
Port input clock setup time
tRCQ
CQCK, RWC, *: See figures 3.
100
ns
Port output data delay time
tCDD
P0 to P4, RWC: See figure 4.
1200
ns
Text readout period
tCW
DQSY, normal speed: See figure 5.
1.5
3.3
3.7
ms
DQSY pulse width
tW
DQSY, normal speed: See figure 5.
60
136
150
µs
SCLK high-level clock pulse width
tWTH
SCLK: See figure 5.
100
ns
SCLK low-level clock pulse width
tWTL
SCLK: See figure 5.
100
ns
SCLK clock delay time
tD1
SCLK: See figure 5.
100
ns
Text data delay time
tD2
SRDT: See figure 5.
50
ns
tD3
SRDT: See figure 5.
50
ns
Reset time
tRES
RES
400
ns
Operating frequency range
fOP
EFMIN
10
MHz
Crystal oscillator frequency
fX
XIN, XOUT
16.9344
MHz




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