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FAN3121T Datasheet(PDF) 4 Page - Fairchild Semiconductor

No. de pieza FAN3121T
Descripción Electrónicos  Application Review and Comparative Evaluation of Low-Side Gate Drivers
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Fabricante Electrónico  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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AN-6069
APPLICATION NOTE
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/6/10
4
Synchronous Rectifier Operation
A MOSFET operated as a synchronous rectifier (SR)
experiences a switching interval significantly different from
the case of a clamped inductive load. Figure 6 shows a
simplified forward converter power stage with a
synchronous rectifier QSR in place of the freewheel diode.
Figure 6.
Simplified Forward Converter
In this example, an SR signal generated by the control
circuit crosses the isolation boundary to keep the
synchronous rectifier QSR on while Q1 is off. However, the
SR signal should command QSR to turn off before Q1 turns
on to apply positive voltage to the transformer. Figure 7
shows four intervals used to illustrate the turn-off sequence
of the synchronous rectifier.
(a)
(b)
(c)
(d)
CGD
CGS
IL
RG
VSEC
VDC
DBD
RLOW
-
+
IG
RDS
S
D
CGD
CGS
CDS
IL
RG
VDC
DBD
RLOW
VSEC
-
+
D
S
VDC
CGD
CGS
CDS
IL
RG
VDC
DBD
RLOW
CGD
CGS
CDS
IL
RG
DBD
RLOW
IG
VSEC
-
+
VSEC
-+
DD
S
S
Figure 7.
SR MOSFET Turn Off
Prior to turn off, the MOSFET conducts load current IL
through the resistive channel RDS and the drain-to-source
voltage is negative. In Figure 7(a) the output of the driver is
low and the combination of CGD and CGS are discharged in
parallel in a time interval given by:
G
SR
,
Q
off
I
Q
t
=
(11)
where QQSR is defined in reference [3] to be:
DD
SR
,
GD
GS
SR
,
Q
V
)
C
C
(
Q
+
=
(12)
Also in reference [3], CGS,SR is estimated as:
DD
SPEC
,
DS
SPEC
,
RSS
SR
,
GD
V
5
.
0
V
C
2
C
=
(13)
From standard MOSFET nomenclature:
RSS
ISS
GS
C
C
C
=
(14)
In Figure 7(b), the MOSFET is fully off, IL flows through
the body diode, and the VSEC polarity has not changed.
When VSEC changes polarity, as shown in Figure 7(c),
current flows from VSEC to recover the body diode stored
charge and the diode commutates. In Figure 7(d), the body
diode has been fully recovered and VDS rises quickly. The
high dV/dT on the MOSFET drain can cause a capacitive
current to flow through the CDS/CGS voltage divider, so a
driver with strong current sink capability is essential to hold
the gate voltage below the threshold voltage.
In the synchronous rectifier application, IG does not affect
switching losses as it did in the clamped inductive load
application. However, the paralleled MOSFETS used in SR
applications require high-current pulses to switch
effectively, and high current drivers are often located in
close proximity.
Transformer Drive Applications
In power converters such as a half-bridge, full-bridge, two-
switch forward converters; and active clamp forward
converters there are high-side switches or a combination of
high/low switches that must be controlled. If galvanic
isolation is not needed between the control and the power
switches, the MOSFETs may be driven with a
semiconductor half-bridge gate driver, but the inherent
propagation delay must be considered in the design. For
circuits that need isolation or can benefit from short
propagation delays, the gate drive transformer should be
considered as a potential solution.
In a related application, it is often necessary to provide high-
speed communication between the primary and secondary
sides of an isolated converter. This can be accomplished
using technologies such as opto-isolators with digital outputs
or magnetic pulse transformers. These pulse transformers
are similar to the gate drive transformer, but they are only
required to transmit logic signals instead of delivering the
high-current pulses to turn a power MOSFET on and off.
The simplified circuit of Figure 8 is used to illustrate the
basic operation of a low-side driver and pulse transformer
used in a communication circuit. The transformer is shown
as ideal transformer with turns ratio NP:NS = 1:1 in parallel


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