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FAN5234MTCX Datasheet(PDF) 9 Page - Fairchild Semiconductor |
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FAN5234MTCX Datasheet(HTML) 9 Page - Fairchild Semiconductor |
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9 / 15 page  © 2004 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5234 • Rev. 2.0.0 9 LD RV PGN D ISN S in+ in- 2.5 V ILIM det. R SE NSE SS 1.5M CSS VSEN Vto I Reference and Soft-Start 17 pf I2 = IL IM *11 ILIM 0.9 V R ILIM ILIM S/ H TO PW M CO M P 3 00K 0 .17p f 4.1 4 K ISNS ISNS Figure 6. Current Limit / Summing Circuits More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET, as shown in Figure 5. This approach causes higher losses, but yields greater accuracy in both VDROOP and ILIMIT. R1 is a low value (e.g. 10m Ω) resistor. Current limit (ILIMIT) should be set high enough to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.2 is sufficient. Since ILIMIT is a peak current cut-off value, multiply ILOAD(MAX) by the inductor ripple current (use 25%). For example, in Figure 1 the target for ILIMIT would be: ILIMIT > 1.2 x 1.25 x 1.6 x 3.5A ≈ 8.5A (6) Duty Cycle Clamp During severe load increase, the error amplifier output can go to its upper limit, pushing a duty cycle to almost 100% for a significant amount of time. This could cause a large increase of the inductor current and lead to a long recovery from a transient over-current condition or even to a failure at high input voltages. To prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output voltage excursion is detected, limiting maximum duty cycle to: ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + = IN V 4 . 2 V V DC IN OUT MAX (7) This is designed to not interfere with normal PWM operation. When FPWM is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. Gate Driver The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals, providing necessary amplification, level shifting, and shoot-through protection. It also has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without concern for simultaneous conduction or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to work properly. Any delay along that path subtracts from the delay generated by the adaptive dead-time circuit and shoot-through may occur. Frequency Loop Compensation Due to the implemented current-mode control, the modulator has a single-pole response with -1 slope at frequency determined by load. Therefore: O OC R 2 1 f PO π = (8) where RO is load resistance and CO is load capacitance. For this type of modulator, type-2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design task, the PWM controller has an internally compensated error amplifier. Figure 7 shows a type two amplifier, its response, and the responses of a current mode modulator and the converter. The type-2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. |
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