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AD6641BCPZ-500 Datasheet(PDF) 3 Page - Analog Devices |
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AD6641BCPZ-500 Datasheet(HTML) 3 Page - Analog Devices |
3 / 28 page AD6641 Rev. 0 | Page 3 of 28 The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS. The ADC requires a 1.9 V analog voltage supply and a differen- tial clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabri- cated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. High Performance ADC Core. Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. 2. Low Power. Consumes only 695 mW at 500 MSPS. 3. Ease of Use. On-chip 16k FIFO allows the user to target the high perfor- mance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip refer- ence and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design. 4. Serial Port Control. Standard serial port interface supports configuration of the device and customization for the user’s needs. 5. 1.9 V or 3.3 V SPI and Serial Data Port Operation. |
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