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ADIS16407 Datasheet(PDF) 5 Page - Analog Devices |
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ADIS16407 Datasheet(HTML) 5 Page - Analog Devices |
5 / 24 page ADIS16407 Rev. A | Page 5 of 24 Parameter Test Conditions/Comments Min Typ Max Unit CONVERSION RATE SPS xGYRO_OUT, xACCL_OUT, xMAGN_OUT SMPL_PRD = 0x0001 819.2 SPS BAR_OUT, BARO_OUTL9 SMPL_PRD = 0x0001 51.2 SPS Clock Accuracy ±3 % Sync Input Clock10 0.8 1.1 kHz POWER SUPPLY Operating voltage range, VDD 4.75 5.0 5.25 V Power Supply Current 70 mA Sleep mode 1.4 mA 1 The extended pressure range is guaranteed by design. 2 See Table 22 for the BAR_OUTL register details, which offer additional digital resolution improvements. 3 The relative error assumes that the initial error, at +25°C, is corrected in the end application. 4 Linearity errors assume a full scale (FS) of 1000 mbar. 5 The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant. 6 Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C. 7 The data retention lifetime equivalent is at a junction temperature (TJ) of 85°C as per JEDEC Standard 22, Method A117. Data retention lifetime decreases with junction temperature. 8 These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may affect overall accuracy. 9 The BARO_OUT and BARO_OUTL registers sample at a rate that is 1/16th that of the other output registers. 10 The sync input clock functions below the specified minimum value, but at reduced performance levels. |
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