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DAC3482IRKDT Datasheet(PDF) 11 Page - Texas Instruments

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No. de pieza DAC3482IRKDT
Descripción Electrónicos  Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC)
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DAC3482IRKDT Datasheet(HTML) 11 Page - Texas Instruments

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DAC3482
www.ti.com
SLAS748A
– MARCH 2011 – REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS
– DIGITAL SPECIFICATIONS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING(3)
Setup time, OSTRP/N
ts(OSTR)
valid to rising edge of
0
ps
DACCLKP/N
Hold time, OSTRP/N
th(OSTR)
valid after rising edge of
300
ps
DACCLKP/N
TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING (4)
Setup time, SYNCP/N
ts(SYNC_PLL)
valid to rising edge of
200
ps
DACCLKP/N
Hold time, SYNCP/N
th(SYNC_PLL)
valid after rising edge of
300
ps
DACCLKP/N
TIMING SERIAL PORT
Setup time, SDENB to
ts(SDENB)
20
ns
rising edge of SCLK
Setup time, SDIO valid to
ts(SDIO)
10
ns
rising edge of SCLK
Hold time, SDIO valid to
th(SDIO)
5
ns
rising edge of SCLK
Register config6 read (temperature sensor read)
1
µs
t(SCLK)
Period of SCLK
All other registers
100
ns
Data output delay after
td(Data)
10
ns
falling edge of SCLK
Minimum RESETB pulse
tRESET
25
ns
width
(3)
OSTR is required in Dual Sync Sources mode. In order to minimize the skew it is recommended to use the same clock distribution
device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC3482 devices in the system.
Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship.
(4)
SYNC is required to synchronize the PLL circuit in multiple devices. The SYNC signal must meet the timing relationship with respect to
the reference clock (DACCLKP/N) of the on-chip PLL circuit.
Copyright
© 2011, Texas Instruments Incorporated
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