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TPS54429PWP Datasheet(PDF) 7 Page - Texas Instruments

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No. de pieza TPS54429PWP
Descripción Electrónicos  7V to 18V Input, 4.5-A Synchronous Step-Down ( SWIFT?? Converter
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS54429PWP Datasheet(HTML) 7 Page - Texas Instruments

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Tss(ms)=
C6(nF) Vref
Iss( A)
µ
=
C6(nF) 0.765
2
TPS54429
www.ti.com
SLVSAS1
– FEBRUARY 2011
OVERVIEW
The TPS54429 is a 4.5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2
™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54429 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2
™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2
™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54429 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54429 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 2-
μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is
2
μA.
(1)
The TPS54429 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
Power Good
The TPS54429 has a power-good open drain output. The power good function is activated after soft start has
finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage is
within -10% of the target value, internal comparators detect power good state and the power good signal
becomes high. If the PG output is pulled up to VREG5, the resister value, which is connected between PG and
VREG5, must be in the range of 20k ohm to 150k ohm. If the feedback voltage goes under 15% of the target
value, the power good signal becomes low after a 5
μs internal delay.
© 2011, Texas Instruments Incorporated
7
Product Folder Link(s) :TPS54429


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