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TPS62361B Datasheet(PDF) 6 Page - Texas Instruments |
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TPS62361B Datasheet(HTML) 6 Page - Texas Instruments |
6 / 51 page t f HIGH S SDA SCL t hd;STA t hd;DAT t r t LOW t su;DAT t f t hd;STA t hd;STA t su;STO t r Sr P S t BUF t fDA t su;STA Sr P Sr = MCS Current Source Pull-Up = R(P) Resistor Pull-Up SDAH SCLH Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit. See Note A See Note A t hd;STA t rDA t hd;DAT t fCL t fCL1 t fCL t su;DAT t LOW t HIGH t LOW t HIGH t rCL1 t su;STO TPS62360, TPS62361B, TPS62362 SLVSAU9 – MAY 2011 www.ti.com I 2C INTERFACE TIMING REQUIREMENTS(1)(2) (continued) PARAMETER TEST CONDITIONS MIN MAX UNIT Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns tRDA Rise time of SDA signal High-speed mode, CB – 100 pF max 10 80 ns High-speed mode, CB – 400 pF max 20 160 ns Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns tFDA Fall time of SDA signal High-speed mode, CB – 100 pF max 10 80 ns High-speed mode, CB – 400 pF max 20 160 ns Standard mode 4 μs tSU, tSTO Setup time for STOP condition Fast mode 600 ns High-speed mode 160 ns CB Capacitive load for SDA and SCL 400 pF I 2C TIMING DIAGRAMS Figure 1. Serial Interface Timing for F/S Mode Figure 2. Serial Interface Timing for H/S Mode 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 |
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