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TPS65180BRGZR Datasheet(PDF) 11 Page - Texas Instruments |
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TPS65180BRGZR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 44 page SLEEP ACTIVE Rails = ON I2C = YES POWER DOWN NOTES: ||, & = logic OR, logic AND. (?), ( ) = rising edge, falling edge. FAULT = UVLO || TSD (thermal shutdown)|| BOOST UV. (*) = Power sequencing is register controlled . (**) = Power sequencing is GPIO controlled . WAKEUP ( ) & All PWRx pins= low All rails = OFF I2C = NO Registers à default Battery removed STANDBY WAKEUP = high & (ACTIVE bit= 1 (*) || any PWRx pin( ) (**)) All rails = OFF I2C = YES WAKEUP = high & (STANDBY bit = 1 (*) || all PWRx pins= (?) (**) || FAULT (**)) WAKEUP (?) TPS65180, TPS65181, TPS65180B, TPS65181B www.ti.com SLVSA76F – MARCH 2010 – REVISED FEBRUARY 2011 Figure 1. Global State Diagram WAKE-UP AND POWER UP SEQUENCING The TPS65180/TPS65181 and TPS65180B/TPS65181B support flexible power-up sequencing through GPIO control using the PWR3, 2, 1, 0 pins or I2C control using the PWR_SEQ0, 1, 2 registers. Using GPIO control, the output rails are enabled/disabled in the order in which the PWRx pins are asserted/de-asserted, respectively, and the power-up timing is controlled by the host only. In I2C control mode the power-up/down order and timing are defined by user register settings. The default settings support the E Ink® Vizplex ™ panel and typically do not need to be charged by the user. © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TPS65180 TPS65181 TPS65180B TPS65181B |
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