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BU6520KV-E2 Datasheet(PDF) 10 Page - Rohm |
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BU6520KV-E2 Datasheet(HTML) 10 Page - Rohm |
10 / 19 page Technical Note 10/18 BU6520KV,BU6521KV www.rohm.com 2010.02 - Rev.C © 2010 ROHM Co., Ltd. All rights reserved. 3. 2-line Serial Interface Timing tLOW SDA SDC tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tHD;ST tSU;STO tBUF Fig.7 2-line Serial Interface Timing Symbol Description MIN TYP MAX Unit fSCL SDC Clock Frequency 0 - 400 kHz tHD;STA Hold Time (repetition) ”START” conditions. The first clock pulse is generated after this period. 0.6 - - µs fLOW The ”L” period of SDC clock 1.3 - - µs tHIGH The ”H” period of SDC clock 0.6 - - µs tSU;STA Setup Time of repetitive ”START” conditions 0.6 - - µs tHD;DAT Data Hold Time 0 µs tSU;DAT Data Setup Time 100 - - ns tSU;STO Setup Time of the ”STOP” conditions 0.6 - - µs tBUF Bus free Time between ”STOP” conditions and the ”START” conditions 1.3 - - µs |
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Descripción similar - BU6520KV-E2 |
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