TS3809/3810 Series

Microprocessor Reset Circuit

4/7

Version: C07

Application Information

Negative-Going VCC transients in addition to issuing a reset to the µP during power-up, power-down, and brownout

conditions, the TS3809/3810 are relatively immune to short-duration negative-going Vcc transients (glitches).

The TS3809/3810 do not generate a reset pulse. The graph was generated using a negative going pulse applied to

Vcc, starting 0.5V above the actual reset threshold and ending below it by the magnitude indicated (reset comparator

overdrive). The graph indicates the maximum pulse width a negative going Vcc transient can have without causing a

reset pulse. As the magnitude of the transient increases (goes farther below the reset threshold), the maximum

allowable pulse width decreases. Typically, a Vcc transient that goes 100mV below the reset threshold and lasts

20µS or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as possible to the Vcc pin

provides additional transient immunity.

Function Description

A microprocessor’s (µP’s) reset input starts the µP In a know state. The TS3809/3810 assert reset to prevent code-

execution errors during power-up, power-down, or brownout conditions. They assert a reset signal whenever the Vcc

supply voltage declines below a preset threshold, keeping it asserted for at least 140ms after Vcc has risen above

the reset threshold. The TS3809/3810 have a push-pull output stage.

Ensuring a Valid Reset Output Down to Vcc=0

RESET is guaranteed to be a logic low for VCC > 1.0V. Once VCC exceeds the reset threshold, an internal timer

keeps RESET low for the reset timeout period; after this interval, RESET goes high. If a brownout condition occurs

(VCC dips below the reset threshold), RESET goes low. Any time VCC goes below the reset threshold, the internal

timer resets to zero, and RESET goes low. The internal timer starts after VCC returns above the reset threshold, and

RESET remains low for the reset timeout period. When Vcc falls below 1V, the TS3809/3810 reset output no longer

sinks current - it becomes an open circuit. Therefore, high impedance CMOS logic input connected to reset can drift

to undetermined voltages. This present no problem in most applications since most µP and other circuitry is

inoperative with Vcc below 1V.However, in applications where reset must be valid down to 0V, adding a pull down

resistor to reset causes and stray leakage currents to flow to ground, holding reset low (Figure 2.) R1’s value is not

critical; 100K is large enough not to load reset and small enough to pull RESET to ground. For the TS3809/3810 if

reset is required to remain valid for Vcc<1V.

Benefits of Highly Accurate Reset Threshold

Most µP supervisor ICs has reset threshold voltages between 5% and 10% below the value of nominal supply

voltages. This ensures a reset will not occur within 5% of the nominal supply, but will occur when the supply is 10%

below nominal. When using ICs rated at only the nominal supply ±5%, this leaves a zone of uncertainty where the

supply is between 5% and 10% low, and where the reset many or may not be asserted

Timming Diagram