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SM5M2 Datasheet(PDF) 3 Page - Sharp Corporation |
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SM5M2 Datasheet(HTML) 3 Page - Sharp Corporation |
3 / 28 page SM5M2 - 3 - P00-P03 PIN DESCRIPTION PIN NAME I/O FUNCTION GND, VDD, VDSP, VR I Power supply pins. The VDD, VDSP, VR pins apply a positive supply with respect to the GND. T, TOSC, VOSC I LSI chip test pins. Cannot be used by the user. Connect T and TOSC to GND. Connect VOSC to VDD. RESET I Input pin with built-in pull-up resistor. Hardware-reset the LSI chip when a Low level signal is input. Normally, a capacitor is connected between it and GND to form a power-on reset circuit. OSCIN, OSCOUT I/O I O Crystal oscillator pins. Connect a crystal oscillator accross [OSCIN-OSCOUT ] to form a clock generator circuit. RC oscillator pins. Connect a resistor across [CK1-VDD ] to form a clock generator circuit. CK2 is used to test its clock out. Voice output pin. Output the contents of a voice ROM. F CK1, CK2 Voice O Melody output pin. Outputs the contents of a melody ROM with standard 12 musical scales (555 to 2 114 Hz) in two octaves. H0-H3 O Pins for the LCD's common signals. S0-S33 O Pins for the LCD's segment signals. INTA I Input pin for external interrupt. The IFA flag is set at the rising edge of INTA. O Output ports. The P0 ports are an output port. The accumulator ACC can be transferred to this port by instruction. P10-P13, P20-P22 I/O P1 and P2 are I/O pins which can switch to input or output pins in 4/3-bit units by instruction. They can be used as output pins when configured for a key matrix. The SM5M2 is forced to hardware-reset when all of P10-P13 pins are High level. (By mask option) |
Número de pieza similar - SM5M2 |
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Descripción similar - SM5M2 |
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