GS4910B datasheet(18/119 Pages) GENNUM

No. de pieza	GS4910B

Descripción Electrónicos	HD/SD/Graphics Clock and Timing Generator with GENLOCK

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Fabricante Electrónico	GENNUM [Gennum Corporation]

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18 / 119 page

GS4911B/GS4910B HD/SD/Graphics Clock and Timing

Generator with GENLOCK

Data Sheet

36655 - 5

June 2009

18 of 119

56JTAG/HOST

Non

Synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to select JTAG Test Mode or Host Interface Mode.

When set HIGH, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI

are configured for JTAG boundary scan testing.

When set LOW, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI are

configured as GSPI pins for normal host interface operation.

57

SCLK_TCLK

Non

Synchronous

Input

SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Clock / Test Clock.

All JTAG / Host Interface address and data are shifted into/out of

the device synchronously with this clock.

Host Mode (JTAG/HOST = LOW):

SCLK_TCLK operates as the host interface serial data clock, SCLK.

JTAG Test Mode (JTAG/HOST = HIGH):

SCLK_TCLK operates as the JTAG test clock, TCLK.

58

SDIN_TDI

Synchronous

with

SCLK_TCLK

Input

SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Input / Test Data Input.

Host Mode (JTAG/HOST = LOW):

SDIN_TDI operates as the host interface serial input, SDIN, used to

write address and configuration information to the internal

registers of the device.

JTAG Test Mode (JTAG/HOST = HIGH):

SDIN_TDI operates as the JTAG test data input, TDI.

59

SDOUT_TDO

Synchronous

with

SCLK_TCLK

Output

SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Output / Test Data Output.

Host Mode (JTAG/HOST = LOW):

SDOUT_TDO operates as the host interface serial output, SDOUT,

used to read status and configuration information from the internal

registers of the device.

JTAG Test Mode (JTAG/HOST = HIGH):

SDOUT_TDO operates as the JTAG test data output, TDO.

60

CS_TMSSynchronous

with

SCLK_TCLK

Input

SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Chip Select / Test Mode Select.

Host Mode (JTAG/HOST = LOW):

CS_TMS operates as the host interface chip select, CS, and is active

LOW.

JTAG Test Mode (JTAG/HOST = HIGH):

CS_TMS operates as the JTAG test mode select, TMS, and is active

HIGH.

Table 1-1: Pin Descriptions (Continued)

Number

Name

Timing

Type

Description

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GS4910B Datasheet(PDF) 18 Page - Gennum Corporation

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