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ADUM1251 Datasheet(PDF) 4 Page - Analog Devices |
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ADUM1251 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 12 page  ADuM1250/ADuM1251 Rev. D | Page 4 of 12 AC Specifications1 All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 3.3 V or 5 V, and VDD2 = 3.3 V or 5 V, unless otherwise noted. Refer to Figure 5. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions MAXIMUM FREQUENCY 1000 kHz OUTPUT FALL TIME 5 V Operation 4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = 40 pF, R1 = 1.6 kΩ, CL2 = 400 pF, R2 = 180 Ω Side 1 Output (0.9 VDD1 to 0.9 V) tf1 13 26 120 ns Side 2 Output (0.9 VDD2 to 0.1 VDD2) tf2 32 52 120 ns 3 V Operation 3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = 40 pF, R1 = 1.0 kΩ, CL2 = 400 pF, R2 = 120 Ω Side 1 Output (0.9 VDD1 to 0.9 V) tf1 13 32 120 ns Side 2 Output (0.9 VDD2 to 0.1 VDD2) tf2 32 61 120 ns PROPAGATION DELAY 5 V Operation 4.5 ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0 pF, R1 = 1.6 kΩ, R2 = 180 Ω Side 1-to-Side 2, Rising Edge2 tPLH12 95 130 ns Side 1-to-Side 2, Falling Edge3 tPHL12 162 275 ns Side 2-to-Side 1, Rising Edge4 tPLH21 31 70 ns Side 2-to-Side 1, Falling Edge5 tPHL21 85 155 ns 3 V Operation 3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = CL2 = 0 pF, R1 = 1.0 kΩ, R2 = 120 Ω Side 1-to-Side 2, Rising Edge2 tPLH12 82 125 ns Side 1-to-Side 2, Falling Edge3 tPHL12 196 340 ns Side 2-to-Side 1, Rising Edge4 tPLH21 32 75 ns Side 2-to-Side 1, Falling Edge5 tPHL21 110 210 ns PULSE WIDTH DISTORTION 5 V Operation 4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0 pF, R1 = 1.6 kΩ, R2 = 180 Ω Side 1-to-Side 2, |tPLH12 − tPHL12| PWD12 67 145 ns Side 2-to-Side 1, |tPLH21 − tPHL21| PWD21 54 85 ns 3 V Operation 3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = CL2 = 0 pF, R1 = 1.0 kΩ, R2 = 120 Ω Side 1-to-Side 2, |tPLH12 − tPHL12| PWD12 114 215 ns Side 2-to-Side 1, |tPLH21 − tPHL21| PWD21 77 135 ns COMMON-MODE TRANSIENT IMMUNITY6 |CMH|, |CML| 25 35 kV/µs 1 All voltages are relative to their respective ground. 2 tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDD2. 3 tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V. 4 tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDD1. 5 tPHL21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V. 6 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. |
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