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ADS4229IRGCR Datasheet(PDF) 10 Page - Texas Instruments |
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ADS4229IRGCR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 67 page  Input Clock CLKOUTM CLKOUTP OutputData DAnP/M,DBnP/M (2) DDR LVDS N 16 - CLKOUT OutputData DAn,DBn Parallel CMOS Input Signal Sample N N +1 t H CLKP CLKM t SU t PDI N 15 - N 14 - N 13 - N 1 - N N+1 16ClockCycles (1) N 16 - N 15 - N 14 - N 13 - N 1 - N N+1 N 12 - 16ClockCycles (1) t SU t H t PDI t A N +2 N +3 N +4 N +16 N +17 N +18 O O O O O O O O O O E E E E E E E E E E E ADS4229 SBAS550A – JUNE 2011 – REVISED OCTOBER 2011 www.ti.com (1) ADC latency after reset. At higher sampling frequencies, tPDI is greater than one clock cycle, which then makes the overall latency = ADC latency + 1. (2) E = even bits (D0, D2, D4, etc.); O = odd bits (D1, D3, D5, etc.). Figure 3. Latency Timing Diagram 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4229 |
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