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SI2324DS Datasheet(PDF) 1 Page - Vishay Siliconix |
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SI2324DS Datasheet(HTML) 1 Page - Vishay Siliconix |
1 / 4 page Document Number: 63245 www.vishay.com S11-1189-Rev. A, 27-Jun-11 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 N-Channel 100 V (D-S) MOSFET SPICE Device Model Si2324DS Vishay Siliconix DESCRIPTION The attached SPICE model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C to + 125 °C temperature ranges under the pulsed 0 V to 10 V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) •Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the - 55 °C to + 125 °C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics SUBCIRCUIT MODEL SCHEMATIC Note • This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to the appropriate datasheet of the same number for guaranteed specification limits. D S DBD CGS M1 G 3 R1 M2 Gx RG CGD Gy ETCV + – |
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