PWRGD

VIN

PGND

PH

VOUT

RT/CLK

VADJ

STSEL

SS/TR

VSENSE+

TPS84410

PWRGD

Logic

+

+

VREF

Comp

Power

Stage

and

Control

Logic

Thermal Shutdown

Shutdown

Logic

VIN

UVLO

OSC w/PLL

INH/UVLO

AGND

OCP

TPS84410

www.ti.com

SLVSAR5

– SEPTEMBER 2011

ELECTRICAL CHARACTERISTICS (continued)

Over -40

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Ceramic

External input capacitance

µF

Non-ceramic

Ceramic

150

µF

External output capacitance

Non-ceramic

Equivalent series resistance (ESR)

25

m

Ω

(5)

A minimum of 47

µF of ceramic capacitance is required across the input for proper operation. Locate the capacitor close to the device.

An additional 220

µF of bulk capacitance is recommended. See Table 5 for more details.

(6)

The amount of required output capacitance varies depending on the output voltage (see Table 3 ). The amount of required capacitance

must include at least 47

µF of ceramic capacitance. Locate the capacitance close to the device. Adding additional capacitance close to

the load improves the response of the regulator to load transients. See Table 3 and Table 5 for more details.

(7)

When using both ceramic and non-ceramic output capacitance, the combined maximum must not exceed 2200

µF.

DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAM

Copyright

© 2011, Texas Instruments Incorporated

5