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TC62D748AFG Datasheet(PDF) 6 Page - Marktech Corporate |
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TC62D748AFG Datasheet(HTML) 6 Page - Marktech Corporate |
6 / 19 page TC62D748AFG/AFNAG/BFNAG 2010-03-05 6 Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating *1 Unit Pow e r su pply volt age VDD −0.3 to 6.0 V Outpu t curr ent IOUT 95 mA Logic in put volt age VIN −0.3 to VDD + 0.3 *2 V Outpu t vo lt age VOUT −0.3 to 17 V Operating temperature Topr −40 to 85 °C S t orage temperat ure Tstg −55 to 150 °C Ther mal resist ance Rth(j-a) 94 (AFG) *3, 80.07(AFNAG/BFNAG) When mounted PCB °C/W Pow e r di ss ip a t ion PD*4 1.32 (AFG) *3, 1.56(AFNAG/BFNAG) When mounted PCB W Note1: Voltage is ground referenced. Note2: Do not exceed 6.0V. Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming) Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each degree (1°C) that the ambient temperature is exceeded (Ta = 25°C). Operating Conditions DC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C) Characteristics Symbol Test Conditions Min Typ. Max Unit Pow e r su pply volt age VDD ⎯ 3.0 ⎯ 5.5 V High level logic input voltage VIH SIN,SCK, SLAT , OE 0.7 × VDD ⎯ VDD V Low le ve l lo gi c inp u t vo l t age VIL SIN,SCK, SLAT , OE GND ⎯ 0.3 × VDD V High level SOUT output current IOH ⎯ ⎯ ⎯ −1 mA Low level SOUT output current IOL ⎯ ⎯ ⎯ 1 mA Const a nt curre nt ou tput IOUT OUTn 1.5 ⎯ 90 mA AC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C) Characteristics Symbol Test Circuits Test Conditions Min Typ. Max Unit Serial data tr ansfer freque ncy fSCK 6 ⎯ ⎯ ⎯ 25 MHz tHOLD1 6 ⎯ 5 ⎯ ⎯ ns Hol d t i me tHOLD2 6 ⎯ 5 ⎯ ⎯ ns tSETUP1 6 ⎯ 5 ⎯ ⎯ ns Setup time tSETUP2 6 ⎯ 5 ⎯ ⎯ ns Maximum clock rise t i me tr 6 *1 ⎯ ⎯ 500 ns Maximum clock fa ll t i me tf 6 *1 ⎯ ⎯ 500 ns Note1: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform,it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind when designing your application. |
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