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CD4541L-D14-T Datasheet(PDF) 5 Page - Unisonic Technologies |
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CD4541L-D14-T Datasheet(HTML) 5 Page - Unisonic Technologies |
5 / 7 page CD4541 CMOS IC UNISONICTECHNOLOGIESCO.,LTD 5 of 7 www.unisonic.com.tw QW-R502-037.C OPERATING CHARACTERISTICS With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a “1”. Both types of reset will result in synchronously resetting all counter stages independent of counter state. The RC oscillator frequency is determined by the external RC network, i.e.: and RS ~ 2 RTC where RS≧10 kΩ The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (2 8, 210, 213, and 2 16). The 2n counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter. When A is “1”, 2 16 is selected for both states of B. However, when B is “0”, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 2 8). The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition and Q/Q select pin is set to a “0” the Q output is a “0”. Correspondingly, when Q/Q select pin is set to a “1” the Q output is a “1”. When the mode control pin is set to a “1”, the selected count is continually transmitted to the output. But, with mode pin “0” and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after 2 n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n-1 counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. INTERNAL RESET RTC 21 RS TO CLOCK CIRCUIT Oscillator Circuit Using RC Configuration 3 CTC |
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