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MCM6708AJ8R2 Datasheet(PDF) 6 Page - Motorola, Inc |
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MCM6708AJ8R2 Datasheet(HTML) 6 Page - Motorola, Inc |
6 / 8 page MCM6708A 2–6 MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) MCM6708A–8 MCM6708A–10 MCM6708A–12 Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 8 — 10 — 12 — ns 3 Address Setup Time tAVEL 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 8 — 9 — 10 — ns Chip Enable to End of Write tELEH, tELWH 7 — 8 — 9 — ns 4, 5 Data Valid to End of Write tDVEH 4 — 5 — 6 — ns Data Hold Time tEHDX 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition. WRITE CYCLE 2 DATA VALID HIGH–Z tAVAV tAVEH tAVEL tELWH tEHAX tDVEH tEHDX A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D (DATA IN) Q (DATA OUT) tELEH |
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