AD6672

Rev. 0 | Page 7 of 32

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,

DCS enabled, unless otherwise noted.

Table 3.

Parameter

Temperature

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

0.9

V

Differential Input Voltage

Full

0.3

3.6

V p-p

Input Voltage Range

Full

AGND

AVDD

V

Input Common-Mode Range

Full

0.9

1.4

V

High Level Input Current

Full

10

+22

μA

Low Level Input Current

Full

−22

−10

μA

Input Capacitance

Full

4

pF

Input Resistance

Full

12

15

18

kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage

Full

1.22

2.1

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

50

71

μA

Low Level Input Current

Full

−5

+5

μA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUT (SCLK)2

High Level Input Voltage

Full

1.22

2.1

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

45

70

μA

Low Level Input Current

Full

−5

+5

μA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUTS (SDIO)1

High Level Input Voltage

Full

1.22

2.1

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

45

70

μA

Low Level Input Current

Full

−5

+5

μA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

5

pF

DIGITAL OUTPUTS (OR+, OR−)

LVDS Data and OR Outputs

Full

250

350

450

mV

Full

1.15

1.25

1.35

V

Full

150

200

280

mV

Full

1.15

1.25

1.35

V