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AD9557BCPZ Datasheet(PDF) 10 Page - Analog Devices |
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AD9557BCPZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 92 page AD9557 Data Sheet Rev. A | Page 10 of 92 Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT TIMING SKEW 10 pF load Between OUT0 and OUT1 10 70 ps HSTL mode on both drivers; rising edge only; any divide value Additional Delay on One Driver by Changing Its Logic Type HSTL to LVDS −5 +1 +5 ps Positive value indicates that the LVDS edge is delayed relative to HSTL HSTL to 1.8 V CMOS −5 0 +5 ps Positive value indicates that the CMOS edge is delayed relative to HSTL OUT1 HSTL to OUT0 3.3 V CMOS, Strong Mode 3.53 3.59 ns The CMOS edge is delayed relative to HSTL 1 The listed values are for the slower edge (rise or fall). TIME DURATION OF DIGITAL FUNCTIONS Table 11. Parameter Min Typ Max Unit Test Conditions/Comments TIME DURATION OF DIGITAL FUNCTIONS EEPROM-to-Register Download Time 13 20 ms Using default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E3F) Register-to-EEPROM Upload Time 138 145 ms Using default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E3F Minimum Power-Down Exit Time 1 ms Time from power-down exit to system clock lock detect |
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