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MCM67A618BFN10 Datasheet(PDF) 6 Page - Motorola, Inc |
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MCM67A618BFN10 Datasheet(HTML) 6 Page - Motorola, Inc |
6 / 12 page MCM67A618B 6 MOTOROLA FAST SRAM ASYNCHRONOUS WRITE CYCLE TIMING (See Notes 1, 2, and 3) MCM67A618B–10 MCM67A618B–12 MCM67A618B–15 Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Times tAVAV 10 — 12 — 15 — ns 4 Setup Times: Address Valid to End of Write Address Valid to E High Address Valid to W Low Address Valid to E Low DataValid to W High Data Valid E High tAVWH tAVEH tAVWL tAVEL tDVWH tDVEH 9 9 0 0 5 5 — — — — — — 10 10 0 0 6 6 — — — — — — 13 13 0 0 7 7 — — — — — — ns Hold Times: W High to Address Invalid E High to Address Invalid W High to Data Invalid E High to Data Invalid tWHAX tEHAX tWHDX tEHDX 0 0 0 0 — — — — 0 0 0 0 — — — — 0 0 0 0 — — — — ns Write Pulse Width: Write Pulse Width (G Low) Write Pulse Width (G High) Write Pulse Width Enable to End of Write Enable to End of Write tWLWH tWLWH tWLEH tELWH tELEH 9 8 9 9 9 — — — — — 10 9 10 10 10 — — — — — 13 12 13 13 13 — — — — — ns 5 6 5, 6 Output Buffer Control: W High to Output Active W Low to Output High–Z tWHQX tWLQZ 3 — — 5 3 — — 6 3 — — 9 ns 7 7, 8 NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. AL and DL are equal to VIH for all asynchronous cycles. 3. Both Write Enables must be equal to VIH for all address transitions. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. If E goes high coincident with or before W goes high the output will remain in a high impedance state. 6. If E goes low coincident with or after W goes low the output will remain in a high impedance state. 7. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tWLQZ is less than tWHQX for a given device. 8. If G goes low coincident with or after W goes low the output will remain in a high impedance state. |
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