1

2

3

4

5

6

7

8

DRVH

SW

VDD

DRVL

BST

SKIP

PWM

GND

TPS51601A

TPS51601A

www.ti.com

SLUSAP3 – MAY 2012

DEVICE INFORMATION

QFN (DRB) PACKAGE

8 PINS

(TOP VIEW)

PIN FUNCTIONS

PIN

I/O

DESCRIPTION

NAME

BST

I

High-side, N-channel FET bootstrap voltage input, supply for high-side driver

DRVH

O

High-side, N-channel FET gate drive output.

DRVL

O

Low-side, synchronous N-channel FET gate drive output

GND

–

Low-side, synchronous N-channel FET gate drive return and device ground.

PWM input. This defines the on-time for the high-side FET of the converter. Input is coming from PWM controller. A

PWM

I

3-state voltage on this pin turns OFF both the high-side (DRVH) and low-side drivers (DRVL)

PwrPAD

–

Thermal pad. This is a non-electrical pad and is recommended to be connected to GND.

If SKIP is LOW, then the inductor current zero-crossing is active and DRVL turns off when inductor current goes to

SKIP

I

zero. (discontinuous conduction mode active)

If SKIP is HIGH, then the DRVL stays HIGH as long as PWM stays LOW. (forced continuous conduction mode)

SW

I/O

High-side N-channel FET gate drive return. Also used as input for sensing inductor current for zero-crossing.

VDD

I

5-V power supply input for the device.

Copyright © 2012, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Link(s): TPS51601A