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TPS71523DCKRG4 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS71523DCKRG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 16 page ABSOLUTE MAXIMUM RATINGS (1) (2) DISSIPATION RATING TABLE TPS715xx SLVS338P – MAY 2001 – REVISED NOVEMBER 2008 .................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT VOUT (2) TPS715xxyyyz XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable). YYY is package designator. Z is package quantity. (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Output voltages from 1.25 V to 5.4 V in 50-mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. Over operating temperature range (unless otherwise noted). UNIT VIN range –0.3 V to +24 V VOUT range –0.3 V to +16.5 V Peak output current Internally limited ESD rating, HBM 2 kV ESD rating, CDM 500 V Continuous total power dissipation See Dissipation Rating Table Junction temperature range, TJ –40°C to +150°C Storage temperature range, Tstg –65°C to +150°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. DERATING FACTOR TA ≤ 25°C TA = +70°C TA = +85°C BOARD PACKAGE RθJC°C/W RθJA°C/W ABOVE TA = +25°C POWER RATING POWER RATING POWER RATING Low-K(1) DCK 165 395 2.52 mW/°C 250 mW 140 mW 100 mW High-K(2) DCK 165 315 3.18 mW/°C 320 mW 175 mW 130 mW (1) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch × 3 inch, two-layer board with 2 ounce copper traces on top of the board. (2) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. 2 Submit Documentation Feedback Copyright © 2001–2008, Texas Instruments Incorporated |
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