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TS3DV621 Datasheet(PDF) 2 Page - Texas Instruments

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No. de pieza TS3DV621
Descripción Electrónicos  12-Channel 1:2 MUX/DEMUX Switch with Integrated 4-Channel Sideband Signal Switching
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TS3DV621 Datasheet(HTML) 2 Page - Texas Instruments

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33
38
36
34
31
29
30
32
2
4
6
8
12
10
14
16
1
3
5
7
11
9
13
15
17
22
24
23
26
28
27
25
D1+A
D3+A
D1–A
D3–A
D2+A
AUX+A
D2–A
AUX–A
D1+B
D3+B
D1–B
D3–B
D2+B
AUX+B
D2–B
AUX–V
VCC
VCC
D0+
D0–
D1+
EN
AUX–
D1–
D2+
D2–
SEL1
SEL2
D3+
D3–
AUX+
HPD
CEC
VCC
GND
TS3DV621
SCDS330B – JANUARY 2012 – REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PIN FUNCTIONS
PIN
I/O TYPE
DESCRIPTION
NAME
NO.
VCC
1,17, 30
Power
Supply Voltage
GND
PowerPad
Ground
Ground
EN
8
I
Enable Input
SEL1
9
I
Select Input 1
SEL2
10
I
Select Input 2
D0+A
41
I/O
Port A, Lane 0, +ve signal
D0-A
39
I/O
Port A, Lane 0, -ve signal
D1+A
38
I/O
Port A, Lane 1, +ve signal
D1-A
36
I/O
Port A, Lane 1, -ve signal
D2+A
34
I/O
Port A, Lane 2, +ve signal
D2-A
32
I/O
Port A, Lane 2, -ve signal
D3+A
29
I/O
Port A, Lane 3, +ve signal
D3-A
27
I/O
Port A, Lane 3, -ve signal
D0+B
42
I/O
Port B, Lane 0, +ve signal
D0-B
40
I/O
Port B, Lane 0, -ve signal
D1+B
37
I/O
Port B, Lane 1, +ve signal
D1-B
35
I/O
Port B, Lane 1, -ve signal
D2+B
33
I/O
Port B, Lane 2, +ve signal
D2-B
31
I/O
Port B, Lane 2, -ve signal
D3+B
28
I/O
Port B, Lane 3, +ve signal
D3-B
26
I/O
Port B, Lane 3, -ve signal
D0+
2
I/O
Common Port, Lane 0, +ve signal
D0–
3
I/O
Common Port, Lane 0, -ve signal
D1+
4
I/O
Common Port, Lane 1, +ve signal
D1–
5
I/O
Common Port, Lane 1, -ve signal
D2+
6
I/O
Common Port, Lane 2, +ve signal
D2–
7
I/O
Common Port, Lane 2, -ve signal
D3+
11
I/O
Common Port, Lane 3, +ve signal
D3-
12
I/O
Common Port, Lane 3, -ve signal
AUX+A
25
I/O
+ve AUX Channel for Port A
AUX-A
23
I/O
-ve AUX Channel for Port A
HPDA
21
I/O
Port A HPD
CECA
19
I/O
Port A CEC
AUX+B
24
I/O
+ve AUX Channel for Port B
AUX-B
22
I/O
-ve AUX Channel for Port B
HPDB
20
I/O
Port B HPD
CECB
18
I/O
Port B CEC
AUX+
13
I/O
+ve AUX Channel for Common Port
AUX–
14
I/O
-ve AUX Channel for Common Port
HPD
15
I/O
HPD for Common Port
CEC
16
I/O
CEC for Common Port
2
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