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TPS659107A1RSL Datasheet(PDF) 63 Page - Texas Instruments |
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TPS659107A1RSL Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 96 page  TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103 TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046N – MARCH 2010 – REVISED APRIL 2012 Bits Field Name Description Type Reset 7 RESERVED Reserved bit RW 1 6 I2CCTLP SDACTL and SCLCTL pull-up control: RW 0 1: Pull-up is enabled 0: Pull-up is disabled 5 I2CSRP SDASR and SCLSR pull-up control: RW 0 1: Pull-up is enabled 0: Pull-up is disabled 4 PWRONP PWRON pad pull-up control: RW 1 1: Pull-up is enabled 0: Pull-up is disabled 3 SLEEPP SLEEP pad pull-down control: RW 1 1: Pull-down is enabled 0: Pull-down is disabled 2 PWRHOLDP PWRHOLD pad pull-down control: RW 1 1: Pull-down is enabled 0: Pull-down is disabled 1 BOOT1P BOOT1 pad control: RW 1 1: Pull-down is enabled 0: Pull-down is disabled 0 BOOT0P BOOT0 pad control: RW 1 1: Pull-down is enabled 0: Pull-down is disabled Table 41. REF_REG Address Offset 0x1D Physical Address Instance Description Reference control register Type RW 7 6 5 4 3 2 1 0 Reserved VMBCH_SEL ST Bits Field Name Description Type Reset 7:4 Reserved Reserved bit RO 0x0 R returns 0s 3:2 VMBCH_SEL Main Battery comparator VMBCH programmable threshold (EEPROM RW 0x0 bits): VMBCH_SEL[1:0] = 00 : bypass VMBCH_SEL[1:0] = 01 : VMBCH = 2.8 V VMBCH_SEL[1:0] = 10 : VMBCH = 2.9 V VMBCH_SEL[1:0] = 11 : VMBCH = 3.0 V 1:0 ST Reference state: RO 0x1 ST[1:0] = 00 : Off ST[1:0] = 01 : On high power (ACTIVE) ST[1:0] = 10 : Reserved ST[1:0] = 11 : On low power (SLEEP) (Write access available in test mode only) Table 42. VRTC_REG Address Offset 0x1E Physical Address Instance Description VRTC internal regulator control register Type RW Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 63 Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104 TPS659105 TPS659106 TPS659107 TPS659108 TPS659109 |
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