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AMS73CAG01808RALJH8H Datasheet(PDF) 4 Page - Advanced Monolithic Systems Ltd |
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AMS73CAG01808RALJH8H Datasheet(HTML) 4 Page - Advanced Monolithic Systems Ltd |
4 / 31 page 4 AMS73CAG01808RA Rev. 1.0 December 2010 Signal Pin Description Pin Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh oper- ation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become stable during the power on and initialization sequence, it must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power- down. Input buffers, excluding CKE, are disabled during Self -Refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS. The ODT pin will be ignored if the Mode Register (MR1) is pro-grammed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-dent with that input data during a Write access. DM is sampled on both edges of DQS. BA0 - BA2 Input Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. A0 - A13 Input Address Inputs: Provided the row address for Active commands and the column address for Read/ Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below)The address inputs also provide the op-code during Mode Register Set commands. A10 / AP Input Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)A10 is sampled during a Precharge command to determine whether the Pre- charge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC Input Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details. RESET Input Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. DQ0 - DQ7 Input/ Output Data Input/ Output: Bi-directional data bus. DQS, DQS Input/ Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS is paired with differential signal DQS to provide differential pair sig- naling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. AMS73CAG01808RA |
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