EN71NS032A0 datasheet(4/10 Pages) EON

No. de pieza	EN71NS032A0

Descripción Electrónicos	Stacked Multi-Chip Product (MCP) Flash Memory and RAM 32 Megabit (2M x 16-bit) CMOS 1.8 Volt-only Burst Simultaneous Operation, Multiplexed Flash Memory and 16 Megabit (1M x 16-bit) Pseudo Static RAM

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Fabricante Electrónico	EON [Eon Silicon Solution Inc.]

Página de inicio	http://www.essi.com.tw

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4 / 10 page

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

4

EN71NS032A0

Rev. B, Issue Date: 2011/07/05

Pin Description

Symbol

Description

Flash

pSRAM

A20–A16

Address Inputs

●

ADQ15–ADQ0

Multiplexed Address/Data

●

OE#

Output Enable input. Asynchronous relative to CLK for the

Burst mode.

●

WE#

Write Enable input.

●

VSSQ/VSS

Ground

●

VCCQ/VCC

Device Power Supply (1.7 V–1.95 V).

●

NC

Not Contact; pin not connected internally

●

RDYf/WAITp

Ready output; indicates the status of the Burst read.

Flash Memory RDY (using default “Active HIGH”

configuration)

VOL = data invalid,

VOH = data valid.

Note: The default polarity for the pSRAM WAIT signal is

opposite the default polarity of the Flash RDY signal.

pSRAM WAIT (using default “Active HIGH” configuration)

VOL = data valid,

VOH = data invalid.

To match polarities, change bit 10 of the pSRAM Bus

Configruation Register to 0 (Active LOW WAIT). Alternately,

change bit 10 of the Flash Configuration Register to 0 (Active

LOW RDY)

●

CLK

Clock input. In burst mode, after the initial word is output,

subsequent active edges of CLK increment the internal

address counter. Should be at VOL or VIH while in

asynchronous mode.

●

AVD#

Address Valid input. Indicates to device that the valid address

is present on the address inputs.

VIL = for asynchronous mode, indicates valid address; for

burst mode, causes starting address to be latched on rising

edge of CLK.

VIH = device ignores address inputs

●

RESET# f

Hardware reset input. VIL = device resets and returns to

reading array data

●

WP#f

Hardware write protect input. VIL = disables program and

erase functions in the four outermost sectors. Should be at VIH

for all other conditions.

●

Vppf

Accelerated input. At Vpp , accelerates programming;

automatically places device in Accelerated Program mode. At

VIL, disables all program and erase functions. Should be at VIH

for all other conditions. (Applying high voltage on MCP

package is prohibited; otherwise, internal RAM may be

damaged easily!)

●

CE# p

Chip Enable Input for pSRAM.

●

CE# f

Chip Enable Input for Flash. Asynchronous relative to CLK for

the Burst mode.

●

CREp

Control register enable (pSRAM).

●

LB#p

Lower byte enable. DQ7~DQ0 (pSRAM)

●

UB#p

Upper byte enable. DQ15~DQ8 (pSRAM)

●

RFU

Reserved for Future Use

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