MCM69F536C

5

MOTOROLA FAST SRAM

Next Cycle

Address

Used

SE1

SE2

SE3

ADSP

ADSC

ADV

G 3

DQx

Write 2, 4

Deselect

None

1

X

X

X

0

X

X

High–Z

X

Deselect

None

0

X

1

0

X

X

X

High–Z

X

Deselect

None

0

0

X

0

X

X

X

High–Z

X

Deselect

None

X

X

1

1

0

X

X

High–Z

X

Deselect

None

X

0

X

1

0

X

X

High–Z

X

Begin Read

External

0

1

0

0

X

X

0

DQ

READ

Begin Read

External

0

1

0

1

0

X

0

DQ

READ

Continue Read

Next

X

X

X

1

1

0

1

High–Z

READ

Continue Read

Next

X

X

X

1

1

0

0

DQ

READ

Continue Read

Next

1

X

X

X

1

0

1

High–Z

READ

Continue Read

Next

1

X

X

X

1

0

0

DQ

READ

Suspend Read

Current

X

X

X

1

1

1

1

High–Z

READ

Suspend Read

Current

X

X

X

1

1

1

0

DQ

READ

Suspend Read

Current

1

X

X

X

1

1

1

High–Z

READ

Suspend Read

Current

1

X

X

X

1

1

0

DQ

READ

Begin Write

Current

X

X

X

1

1

1

X

High–Z

WRITE

Begin Write

Current

1

X

X

X

1

1

X

High–Z

WRITE

Begin Write

External

0

1

0

1

0

X

X

High–Z

WRITE

Continue Write

Next

X

X

X

1

1

0

X

High–Z

WRITE

Continue Write

Next

1

X

X

X

1

0

X

High–Z

WRITE

Suspend Write

Current

X

X

X

1

1

1

X

High–Z

WRITE

Suspend Write

Current

1

X

X

X

1

1

X

High–Z

WRITE

NOTES: 1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.

3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.

4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times.

G must also remain negated at the completion of the write cycle to ensure proper write data hold times.

1st Address (External)

2nd Address (Internal)

3rd Address (Internal)

4th Address (Internal)

X . . . X00

X . . . X01

X . . . X10

X . . . X11

X . . . X01

X . . . X10

X . . . X11

X . . . X00

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X00

X . . . X01

X . . . X10

1st Address (External)

2nd Address (Internal)

3rd Address (Internal)

4th Address (Internal)

X . . . X00

X . . . X01

X . . . X10

X . . . X11

X . . . X01

X . . . X00

X . . . X11

X . . . X10

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X10

X . . . X01

X . . . X00

WRITE TRUTH TABLE

Cycle Type

SGW

SW

SBa

SBb

SBc

SBd

Read

H

H

X

X

X

X

Read

H

L

H

H

H

H

Write Byte a

H

L

L

H

H

H

Write Byte b

H

L

H

L

H

H

Write Byte c

H

L

H

H

L

H

Write Byte d

H

L

H

H

H

L

Write All Bytes

H

L

L

L

L

L

Write All Bytes

L

X

X

X

X

X