Rev. 06/20/02

SP202E Series High Performance RS232 Transceivers

© Copyright 2002 Sipex Corporation

5

The instantaneous slew rate of the transmitter

output is internally limited to a maximum of 30V/

µs in order to meet the standards [EIA RS-232-D

2.1.7, Paragraph (5)]. However, the transition re-

gion slew rate of these enhanced products is typi-

cally 10V/

µs. The smooth transition of the loaded

output from V

tonicity requirements of the standard [EIA

RS-232-D 2.1.7, Paragraphs (1) & (2)].

Receivers

The receivers convert RS-232 input signals to

inverted TTL signals. Since the input is usually

from a transmission line, where long cable lengths

and system interference can degrade the signal, the

inputs have a typical hysteresis margin of 500mV.

This ensures that the receiver is virtually immune

to noisy transmission lines.

The input thresholds are 0.8V minimum and 2.4V

maximum, again well within the

±3V RS-232

requirements. The receiver inputs are also pro-

tected against voltages up to

±15V. Should an

input be left unconnected, a 5KOhm pulldown

resistor to ground will commit the output of the

receiver to a high state.

20

19

R IN

R OUT

2

R

1

34

R IN

R OUT

1

1

18

T IN

2

T OUT

2

2

5

T IN

1

T OUT

1

9

GND

400k Ω

400k Ω

14

13

C +

C -

V-

V-

V+

1

1

11

7

V

CC

+5V INPUT

12

2

1

5k Ω

5k Ω

17

10

C +

C +

C -

C -

2

2

GND

6

8

15

16

2

2

Do not make

connection to

these pins

Internal

-10V Power

Supply

Internal

+10V Power

Supply

SP233ECT

20

19

R IN

R OUT

2

R

1

34

R IN

R OUT

1

1

18

T IN

2

T OUT

2

2

5

T IN

1

T OUT

1

9

GND

400k Ω

400k Ω

13

8

C +

C -

V-

V-

V+

1

1

10

7

V

CC

+5V INPUT

11

2

1

5k Ω

5k Ω

17

12

C +

C +

C -

C -

2

2

GND

6

14

15

16

2

2

Do not make

connection to

these pins

Internal

-10V Power

Supply

Internal

+10V Power

Supply

SP233ECP

Figure 2. Typical Circuits using the SP233ECP and SP233ECT

10

9

R IN

R OUT

2

13

14

R IN

R OUT

1

11

8

T IN

2

T OUT

2

12

15

T IN

1

T OUT

1

16

GND

400k Ω

400k Ω

4

2

C +

C -

1

1

7

17

V

CC

V+

+

+

0.1 F

6.3V

µ

+5V to +10V

Voltage Doubler

+5V INPUT

3

V-

2

1

5k Ω

5k Ω

6

5

C +

C -

2

2

+

0.1 F

16V

µ

+10V to -10V

Voltage Inverter

10 F 6.3V

µ

SP310E

+

18

ON/OFF

+

0.1 µF

16V

*

*The negative terminal of the V+ storage capacitor can be tied

is recommended.

0.1 µF

16V

10

9

R IN

R OUT

2

13

14

R IN

R OUT

1

11

8

T IN

2

T OUT

2

12

15

T IN

1

T OUT

1

16

GND

400k Ω

400k Ω

4

2

C +

C -

1

1

7

17

V

CC

V+

+

+

0.1 F

6.3V

µ

+5V to +10V

Voltage Doubler

+5V INPUT

3

V-

2

1

5k Ω

0.1 F

16V

µ

5k Ω

6

5

C +

C -

2

2

+

0.1 F

16V

µ

+10V to -10V

Voltage Inverter

10 F 6.3V

µ

SP312E

+

18

SHUTDOWN

1

EN

+

0.1 F

16V

µ

*

*The negative terminal of the V+ storage capacitor can be tied

is recommended.

Figure 3. Typical Circuits using the SP310E and SP312E