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MCM69L736AZP7.5R Datasheet(PDF) 3 Page - Motorola, Inc |
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MCM69L736AZP7.5R Datasheet(HTML) 3 Page - Motorola, Inc |
3 / 20 page MCM69L736A •MCM69L818A 3 MOTOROLA FAST SRAM MCM69L736A PIN DESCRIPTIONS PBGA Pin Locations Symbol Type Description 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T SA Input Synchronous Address Inputs: Registered on the rising clock edge. 4K CK Input Address, data in, and control input register clock. Active high. 4L CK Input Address, data in, and control input register clock. Active low. 4M SW Input Synchronous Write: Registered on the rising clock edge, active low. Writes all enabled bytes. 5L, 5G, 3G, 3L (a), (b), (c), (d) SBx Input Synchronous Byte Write Enable: Enables writes to byte x in conjunction with the SW input. Has no effect on read cycles, active low. 4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active low. 4F G Input Output Enable: Asynchronous pin, active low. 2U TMS Input Test Mode Select (JTAG). 3U TDI Input Test Data In (JTAG). 4U TCK Input Test Clock (JTAG). 5U TDO Output Test Data Out (JTAG). 4D ZQ Input Programmable Output Impedance: Programming pin. 7T ZZ Input Reserved for future use. Must be grounded. (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P DQx I/O Synchronous Data I/O. 3J, 5J Vref Supply Input Reference: Provides reference voltage for input buffers. 4C, 2J, 4J, 6J, 4R, 3R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply Output Power Supply: Provides operating power for output buffers. 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 5R VSS Supply Ground. 4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U NC — No Connection: There is no connection to the chip. |
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