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SL74HC123 Datasheet(PDF) 2 Page - System Logic Semiconductor

No. de Pieza. SL74HC123
Descripción  Dual Retriggerable Monostable Multivibrator
Descarga  6 Pages
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Fabricante  SLS [System Logic Semiconductor]
Página de inicio  http://www.slsemicon.co.kr/e_index.htm
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SL74HC123 Datasheet(HTML) 2 Page - System Logic Semiconductor

   
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SL74HC123
System Logic
Semiconductor
SLS
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
A, B, CLR
CX, RX
±20
±30
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
°C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
°C from 65° to 125°C
SOIC Package: : - 7 mW/
°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
3.0
**
6.0
V
VIN, VOUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
-55
+125
°C
tr, tf
Input Rise and Fall Time - CLR
(Figure 2)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
A or B
-
No
Limit
RX
External Timing Resistor
VCC <4.5 V
VCC
≥ 4.5 V
10
2.0
1000
1000
k
CX
External Timing Capacitor
0
No
Limit
µF
**
The In74HC123 will function at 2.0 V but for optimum pulse width stability, VCC should be above
3.0 V.
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND
≤(V
IN or VOUT)
≤V
CC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.


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