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MCM69Q618TQ8 Datasheet(PDF) 1 Page - Motorola, Inc |
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MCM69Q618TQ8 Datasheet(HTML) 1 Page - Motorola, Inc |
1 / 12 page MCM69Q618 1 MOTOROLA FAST SRAM Advance Information 64K x 18 Bit Synchronous Separate I/O Fast SRAM The Motorola MCM69Q618 is a 1 Megabit static random access memory, organized as 64K words of 18 bits. It features separate data input and data output buffers and incorporates input and output registers on board with high speed SRAM. The MCM69Q618 allows the user to perform transparent write and data pass through. Two data bus ports are provided – a data input (D) and a data output (Q) port. The synchronous design allows for precise cycle control with the use of an external single clock (K). Address port, data input (D0 – D17), data output (Q0 – Q17), write en- able (W), chip enables (E1, E2), and pass–through enable (PT) are registered on the rising edge of clock (K). Any given cycle operates on only one address. However, for any cycle, reads and writes can be intermixed. Thus, one can perform a read, a write, or a combination read/ write during any one cycle. For a combination read/write, the contents of the array are read before the new data is written. By using the pass–through function, the output port Q can be made to reflect either the contents of the array or the data presented to the input port D. For read/write or a read cycle with G low, the Q port will output the contents of the array. However, if PT is asserted, the Q port will instead output the data presented at the D input port. • Single 3.3 V ± 5% Power Supply • Fast Access Times: 6/8/10 ns Max • Sustained Throughput of 1.49 Gigabits/Second • Single Clock Operation • Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip • 83 MHz Maximum Clock Cycle Time • Self Timed Write • Separate Data Input and Data Output Pins • Pass–Through Feature • Asynchronous Output Enable (G) • LVTTL Compatible I/O • No Dead Cycles Required for Reads after Writes or for Writes after Reads • 100 Pin TQFP Package • Simultaneous Reads and Writes Suggested Applications — ATM — Ethernet Switches — Routers — Cell/Frame Buffers — SNA Switches — Shared Memory Product Family Configurations Part Number Dual Address Single Address Dual I/O Separate I/O MCM69D536 n Note 1 n Note 2 MCM69D618 n Note 1 n Note 2 MCM69Q536 n n MCM69Q618 n n MCM67Q709 n n MCM67Q909 n n NOTES: 1. Tie AX and AY address ports together for the part to function as a single address part. 2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs. This document contains information on a new product. Specifications and information herein are subject to change without notice. Order this document by MCM69Q618/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM69Q618 TQ PACKAGE 100 PIN TQFP CASE 983A–01 REV 5 11/24/97 © Motorola, Inc. 1997 |
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