54ACT16833, 74ACT16833

DUAL 8BIT TO 9BIT PARITY BUS TRANSCEIVERS

SCAS166A − JUNE 1990 − REVISED APRIL 1996

2

POST OFFICE BOX 655303

POST OFFICE BOX 1443

FUNCTION TABLE

INPUTS

OUTPUT AND I/O

OEB

OEA

CLR

CLK

Ai

Σ OF H

Bi†

Σ OF H

A

B

PARITY

ERR‡

FUNCTION

L

H

X

X

Odd

Even

NA

NA

A

L

H

NA

A data to B bus and

generate parity

H

L

H

↑

NA

Odd

Even

B

NA

NA

H

L

B data to A bus and

check parity

X

X

L

X

X

X

X

NA

NA

H

Check error-flag register

H

No

↑

X

NC

H

H

LNo

↑

X

X

Z

Z

Z

H

Isolation§

H

H

H

↑

Odd

XZ

ZZ

H

Isolation§

H

↑

Even

L

L

L

X

X

Odd

Even

NA

NA

A

H

L

NA

A data to B bus and

generate inverted parity

NA = not applicable, NC = no change, X = don’t care

† Summation of high-level inputs includes PARITY along with Bi inputs.

‡ Output states shown assume ERR was previously high.

§ In this mode, ERR (when clocked) shows inverted parity of the A bus.